Architecture study of a 3D CMOS-NEM FPGA

In this paper, we introduce a reconfigurable architecture, named 3D CMOS-NEM FPGA, which utilizes nanoelectromechanical (NEM) relays and 3D integration techniques synergistically. Unique features of our architecture include: hybrid CMOS-NEM FPGA look-up tables (LUTs) and con gurable logic blocks (CLBs), NEM-based switch blocks (SBs) and connection blocks (CBs), and face-to-face 3D stacking. This architecture also has a built-in feature named direct link which are dedicated local communication channels using the short vertical wires between the two stacks to further enhance performance. A customized 3D FPGA placement and routing flow and a customized cycle-accurate mixed-level power/thermal simulator have been developed. It is shown that 3D stacking together with NEM devices achieves a 33.11% delay reduction, 29.19% power reduction, and 78.23% footprint reduction over the baseline simultaneously, with negligible temperature penalty.

Name thesis:degree_name

M.S.

Level thesis:degree_level

Thesis

Discipline thesis:degree_discipline

Electrical & Computer Engr

Grantor

University of Illinois at Urbana-Champaign

Year dc:date

2013

Author dc:creator

• Li, Chong

Contributors dc:contributor

• Chen, Deming

• Field-Programmable Gate Array (FPGA)
• Architecture

Statement dc:rights

• Copyright 2013 Chong Li

Language dc:language

en

Handle dc:identifier

http://hdl.handle.net/2142/45653

OAI identifier oai:identifier

oai:www.ideals.illinois.edu:2142/45653