{"id":{"repo_id":"uiuc","oai_identifier":"oai:www.ideals.illinois.edu:2142/45653"},"canonical_url":"https://search.dev.ndltd.org/etd/uiuc/oai:www.ideals.illinois.edu:2142/45653","repository":{"repo_id":"uiuc","name":"University of Illinois - Urbana-Champaign","base_url":"https://www.ideals.illinois.edu/oai-pmh"},"display":{"title":"Architecture study of a 3D CMOS-NEM FPGA","abstract":"In this paper, we introduce a reconfigurable architecture, named 3D CMOS-NEM FPGA, which utilizes nanoelectromechanical (NEM) relays and 3D integration techniques synergistically. Unique features of our architecture include: hybrid CMOS-NEM FPGA look-up tables (LUTs) and con gurable logic blocks (CLBs), NEM-based switch blocks (SBs) and connection blocks (CBs), and face-to-face 3D stacking. This architecture also has a built-in feature named direct link which are dedicated local communication channels using the short vertical wires between the two stacks to further enhance performance. A customized 3D FPGA placement and routing flow and a customized cycle-accurate mixed-level power/thermal simulator have been developed. It is shown that 3D stacking together with NEM devices achieves a 33.11% delay reduction, 29.19% power reduction, and 78.23% footprint reduction over the baseline simultaneously, with negligible temperature penalty.","abstract_html":"In this paper, we introduce a reconfigurable architecture, named 3D CMOS-NEM FPGA, which utilizes nanoelectromechanical (NEM) relays and 3D integration techniques synergistically. Unique features of our architecture include: hybrid CMOS-NEM FPGA look-up tables (LUTs) and con gurable logic blocks (CLBs), NEM-based switch blocks (SBs) and connection blocks (CBs), and face-to-face 3D stacking. This architecture also has a built-in feature named direct link which are dedicated local communication channels using the short vertical wires between the two stacks to further enhance performance. A customized 3D FPGA placement and routing flow and a customized cycle-accurate mixed-level power/thermal simulator have been developed. It is shown that 3D stacking together with NEM devices achieves a 33.11% delay reduction, 29.19% power reduction, and 78.23% footprint reduction over the baseline simultaneously, with negligible temperature penalty.","abstract_has_math":false,"creators":["Li, Chong"],"institution":"University of Illinois at Urbana-Champaign","degree_name":"M.S.","degree_level":"Thesis","degree_discipline":"Electrical & Computer Engr","degree_department":null,"school":null,"contributors":["Chen, Deming"],"advisors":[],"committee_chairs":[],"committee_members":[],"year":2013,"date_issued":"2013-08-22T16:56:48Z","date_published":"2013-08-22T16:56:48Z","updated_at":"2026-07-22T22:25:36Z","subjects":["Field-Programmable Gate Array (FPGA)","Architecture"],"languages":["en"],"rights":["Copyright 2013 Chong Li"],"rights_urls":[],"identifier_entries":[]},"links":{"outbound_url":"http://hdl.handle.net/2142/45653","outbound_label":"Handle","outbound_source":"dc:identifier"},"metadata_groups":[{"id":"people","label":"People","entries":[{"key":"dc:contributor","label":"Contributor","values":["Chen, Deming"]},{"key":"dc:creator","label":"Author","values":["Li, Chong"]}]},{"id":"academic_context","label":"Academic Context","entries":[{"key":"dc:date","label":"Dc Date","values":["2013-08-22T16:56:48Z","2015-08-22T10:01:01Z","2013-08"]},{"key":"dc:type","label":"Dc Type","values":["text"]},{"key":"thesis:degree_discipline","label":"Discipline","values":["Electrical & Computer Engr"]},{"key":"thesis:degree_level","label":"Degree Level","values":["Thesis"]},{"key":"thesis:degree_name","label":"Degree Name","values":["M.S."]},{"key":"thesis:institution_name","label":"Thesis Institution Name","values":["University of Illinois at Urbana-Champaign"]}]},{"id":"subjects_keywords","label":"Subjects and Keywords","entries":[{"key":"dc:subject","label":"Dc Subject","values":["Field-Programmable Gate Array (FPGA)","Architecture"]}]},{"id":"language_rights","label":"Language and Rights","entries":[{"key":"dc:language","label":"Dc Language","values":["en"]},{"key":"dc:rights","label":"Dc Rights","values":["Copyright 2013 Chong Li"]}]},{"id":"identifiers","label":"Identifiers","entries":[{"key":"dc:identifier","label":"Identifier","values":["http://hdl.handle.net/2142/45653"]}]},{"id":"additional","label":"Additional Metadata","entries":[{"key":"dc:description","label":"Description","values":["In this paper, we introduce a reconfigurable architecture, named 3D CMOS-NEM FPGA, which utilizes nanoelectromechanical (NEM) relays and 3D integration techniques synergistically. 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Unique features of our architecture include: hybrid CMOS-NEM FPGA look-up tables (LUTs) and con gurable logic blocks (CLBs), NEM-based switch blocks (SBs) and connection blocks (CBs), and face-to-face 3D stacking. This architecture also has a built-in feature named direct link which are dedicated local communication channels using the short vertical wires between the two stacks to further enhance performance. A customized 3D FPGA placement and routing flow and a customized cycle-accurate mixed-level power/thermal simulator have been developed. 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