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Showing 1 to 20 of 36 for “"3D integration"”.

  1. 3D integration of micro- and nanostructures into bio-analytical devices

    This study aims to develop a process which allows 3D integration of micro and nanostructures in microchannels. A fabrication process was established for the large area integration of hierarchical micro and nanostructures in microchannels. This novel process, which is called 3D molding, takes …

    lsu-thes Repository record for 3D integration of micro- and nanostructures into bio-analytical devices (opens in a new tab)

  2. Novel Thin Film Nanogap Device Fabrication And 3D Integration Enabled By Adhesion Lithography

    … oxides, and 2-dimensional/3-dimensional (2D/3D) nano/micro-structure materials play an important role in LAE. Due to the nature of these materials, conventional fabrication processes for Si and its oxides, as well as III-V materials, are not compatible anymore. Many new deposition methods, …

    cambridge Repository record for Novel Thin Film Nanogap Device Fabrication And 3D Integration Enabled By Adhesion Lithography (opens in a new tab)

  3. Designing High-Performance Microprocessors in 3-Dimensional Integration Technology

    … the impact of a new emerging technology called 3D-integration technology on conventional high-performance microprocessors. 3D-integration technology stacks active devices in the vertical dimension in addition to the conventional horizontal dimension. The additional degree of connectivity in the …

    gatech Repository record for Designing High-Performance Microprocessors in 3-Dimensional Integration Technology (opens in a new tab)

  4. ERNI-3D : a technology-generic tool for interconnect reliability projections in 3D integrated circuits

    … This approach is commonly referred to as the 3D integration of ICs. Although there has been significant research on the impact of 3D integration on chip size, interconnect delay, and overall system performance, the reliability issues in the 3D interconnect arrays are largely unknown. In this …

    mit Repository record for ERNI-3D : a technology-generic tool for interconnect reliability projections in 3D integrated circuits (opens in a new tab)

  5. Optimization of Test and Design-for-Testability Solutions for Many-Core System-on-Chip Designs

    … a large and complex system. In addition to NOCs, 3D integration technology using through-silicon-vias (TSVs) can also alleviate the problems caused by long global interconnects and it offers more innovative design choices compared to traditional 2D integrated circuits (ICs).</p><p>Regardless of …

    duke Repository record for Optimization of Test and Design-for-Testability Solutions for Many-Core System-on-Chip Designs (opens in a new tab)

  6. A study of through-silicon-via (TSV) induced transistor variation

    … scaling becomes increasingly difficult, 3D integration has emerged as a viable solution to achieve higher bandwidth and power efficiency. Through-siliconvias (TSVs), which directly connect stacked structures die-to-die, is one of the key techniques enabling 3D integration. The process …

    mit Repository record for A study of through-silicon-via (TSV) induced transistor variation (opens in a new tab)

  7. Design-for-Test and Test Optimization Techniques for TSV-based 3D Stacked ICs

    … to reduce the length of these interconnects, 3D integration</p><p>and 3D stacked ICs (3D SICs) are active areas of research in both academia and industry.</p><p>3D SICs not only have the potential to reduce average interconnect length and alleviate</p><p>many of the problems caused by long …

    duke Repository record for Design-for-Test and Test Optimization Techniques for TSV-based 3D Stacked ICs (opens in a new tab)

  8. Architecture and CAD for nanoscale and 3d FPGA

    … performance is to incorporate three-dimensional (3D) integration, which increases the number of active layers and optimizes the interconnect network vertically. Another solution is to apply novel nanoelectronic materials (nanomaterials) and devices. This dissertation introduces three novel …

    uiuc Repository record for Architecture and CAD for nanoscale and 3d FPGA (opens in a new tab)

  9. Analog-digital co-existence in 3D-IC

    … as process cost increases exponentially. 3D integration has the potential to keep driving performance forward while keeping cost down. The possibility to integrate separate dies with low-parasitic, dense interconnect and shorter routing provides area and power benefits. However, new …

    mit Repository record for Analog-digital co-existence in 3D-IC (opens in a new tab)

  10. Architecture study of a 3D CMOS-NEM FPGA

    … introduce a reconfigurable architecture, named 3D CMOS-NEM FPGA, which utilizes nanoelectromechanical (NEM) relays and 3D integration techniques synergistically. Unique features of our architecture include: hybrid CMOS-NEM FPGA look-up tables (LUTs) and con gurable logic blocks (CLBs), NEM-based …

    uiuc Repository record for Architecture study of a 3D CMOS-NEM FPGA (opens in a new tab)

  11. Packaging of a High Power Density Point of Load Converter

    … dissipate heat without the use of a heat sink. 3D integration techniques are needed to realize a solution that incorporates the active and components together. The objective of this research is to explore the packaging of a high current, high power density, high frequency DC/DC converter using …

    vt Repository record for Packaging of a High Power Density Point of Load Converter (opens in a new tab)

  12. System-Technology Co-Optimization of Scaled Electronics Based on Two-Dimensional Materials

    … dimensions approach the physical limits, and integration density is constrained. This thesis addresses these issues with two-dimensional (2D) materials, which includes inventing a low-temperature (< 300 °C) metal-organic chemical vapor deposition (MOCVD) method for 2D materials on 8-inch …

    mit Repository record for System-Technology Co-Optimization of Scaled Electronics Based on Two-Dimensional Materials (opens in a new tab)

  13. Lab-to-Fab Monolithic 3D Integrated Carbon Nanotube Transistors: Scaling and Reliability

    … promising solution to this problem is monolithic 3D integration, in which layers of compute and memory are designed and integrated together vertically in the same monolithic 3D nanosystem, connected by ultra-dense, nanoscale interconnects, referred to as interlayer vias (ILVs). This provides …

    mit Repository record for Lab-to-Fab Monolithic 3D Integrated Carbon Nanotube Transistors: Scaling and Reliability (opens in a new tab)

  14. Nanowires for 3d silicon interconnection – low temperature compliant nanowire-polymer film for z-axis interconnect

    … has evolved from single chip packaging to 3D heterogeneous system integration using multichip stacking in a single module. One of the key challenges in 3D integration is the high density interconnects that need to be formed between the chips with through-silicon-vias (TSVs) and inter-chip …

    cork Repository record for Nanowires for 3d silicon interconnection – low temperature compliant nanowire-polymer film for z-axis interconnect (opens in a new tab)

  15. High performance MoS₂ transistors based on wafer-scale low-temperature MOCVD synthesis

    … back-end-of-line (BEOL) solutions to improve the integration density and functionality of conventional silicon circuits, two-dimensional (2D) material devices are believed to be very promising, due to their high mobility, relatively large band gaps, atom-level thickness, performance comparable to …

    mit Repository record for High performance MoS₂ transistors based on wafer-scale low-temperature MOCVD synthesis (opens in a new tab)

  16. Low-Profile Magnetic Integration for High-Frequency Point-of-Load Converter

    … high power density POL needs to be developed. An integration solution was recently proposed to incorporate passive components, especially magnetic components, with active components in order to realize the needed power density for the POL. Today's discrete VR only has around 100W/in3 power …

    vt Repository record for Low-Profile Magnetic Integration for High-Frequency Point-of-Load Converter (opens in a new tab)

  17. CMOS-Compatible Wafer-Scale Synthesis and Rapid Characterization of Two-Dimensional Transition Metal Dichalcogenides

    … These contributions collectively advance the integration of 2D TMD materials into CMOS fabrication, enabling monolithic 3D integration in future electronics.

    mit Repository record for CMOS-Compatible Wafer-Scale Synthesis and Rapid Characterization of Two-Dimensional Transition Metal Dichalcogenides (opens in a new tab)

  18. Advanced silicon photonic microcavities for routing, detection and lasing applications

    … such as germanium and silicon nitride, and 3D-integration technologies that were previously exclusive to electronics development, leading to tremendous progress in cavity-based integrated photonic circuits. Using the silicon photonic platform developed by our group, high-performance …

    mit Repository record for Advanced silicon photonic microcavities for routing, detection and lasing applications (opens in a new tab)

  19. Hybrid microfluidic cooling and thermal isolation technologies for 3D ICs

    A key challenge for three dimensional (3D) integrated circuits (ICs) is thermal management. There are two main thermal challenges in typical 3D ICs. First, in the homogeneous integration with multiple high-power tiers, an effective cooling solution that scales with the number of dice in the stack …

    gatech Repository record for Hybrid microfluidic cooling and thermal isolation technologies for 3D ICs (opens in a new tab)

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