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University of Illinois at Urbana-Champaign

The testability of regular logic structures

Abstract

dc:description

The use of regular logic structures has become very important in the recent past due to the complexity of the circuits that are being fabricated and the need to design, test and debug them. The testability of different classes of regular logic structures that are widely used in many practical applications is investigated in this thesis. The first class of circuits that is considered is called generalized counters. These are complex tree-structured circuits and can be represented by recursive mathematical equations. They do not possess rigid topological regularity. The testability of these circuits is investigated under the assumption of single as well as multiple faulty cells. A circuit design methodology is proposed that results in easily testable circuits when single faulty cells are assumed to occur. The second class of circuits examined is that of iterative logic arrays which are widely used in computer arithmetic hardware. The issues of design-for-testability, built-in self-test as well as automatic test generation for these circuits are discussed. The techniques developed are far more powerful and general than those conceived by previous researchers. A test generation program for iterative logic arrays that is the first of its kind to be written is discussed. The test generation problem for one-dimensional sequential arrays of cells is also analyzed. Such arrays, called bit-serial arrays, are widely used in many digital signal processing applications.

Degree

thesis:*
Name thesis:degree_name
Ph.D.
Level thesis:degree_level
Dissertation
Discipline thesis:degree_discipline
Electrical Engineering
Grantor
University of Illinois at Urbana-Champaign
Year dc:date
2011

Author and committee

dc:creator, dc:contributor.*
Author dc:creator
  • Chatterjee, Abhijit
Contributors dc:contributor
  • Abraham, Jacob A.

Subjects

dc:subject × 2

Rights

dc:rights
Statement dc:rights
  • Copyright 1990 Chatterjee, Abhijit
Language dc:language
eng

Identifiers

dc:identifier.*
Identifier
AAI9021660
(UMI)AAI9021660
OAI identifier oai:identifier
oai:www.ideals.illinois.edu:2142/21902

Chain of custody

source
Harvested from
University of Illinois - Urbana-Champaign
Base URL
www.ideals.illinois.edu/oai-pmh
Last updated
2026-07-22
Source record
OAI-PMH GetRecord
citation

Chatterjee, Abhijit. The testability of regular logic structures. Dissertation thesis, University of Illinois at Urbana-Champaign, 2011. http://hdl.handle.net/2142/21902