Global ETD Search
Search theses and dissertations gathered from participating repositories worldwide. Every result links back to the library that holds it. No account is needed.
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Showing 1 to 20 of 30 for “"Built-In Self-Test"”.
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A built-in self-test PLA generator
In this thesis we studied a BIST PLA generator (BPG) which generates BIST PLA layouts from the personality matrix of PLAs. We studied various BIST PLA designs and selected the design proposed by Treur, Fujiwara and Agarwal to be employed by BPG. The BIST PLA design is known to be effective in area …
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New Techniques for Logic Built -in Self -Test
The dissertation investigates new techniques for logic built-in self-test (BIST) in VLSI chip testing. The main purpose of these techniques is to improve fault coverage for logic BIST with minimal performance penalty and hardware overhead. One technique is the method of constrained scan cells. It …
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(VDL)² : a jitter measurement built-in self-test circuit for phase locked loops
… circuit, the (VDL)2, with the purpose of measuring jitter in IBM's phase locked loops. The (VDL)2, which stands for Variable Vernier Digital Delay Locked Line, implements both cycle-to-cycle and phase jitter measurements, by using a digital delay locked loop and a 60 stage Vernier delay line. …
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Techniques for Seed Computation and Testability Enhancement for Logic Built-In Self Test
With the increase of device complexity and test-data volume required to guarantee adequate defect coverage, external testing is becoming increasingly difficult and expensive. Logic Built-in Self Test (LBIST) is a viable alternative test strategy as it helps reduce dependence on an elaborate …
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A SEIR-based ADC built-in-self-test and its application in ADC self-calibration
The static linearity test is one of the fundamental production tests used to measure DC performance of analog to digital converters (ADCs). It comes with high test equipment cost. An ADC built-in-self-test (BIST) is an attractive solution. However the stringent linearity requirement for an on-chip …
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An investigation into self-test concepts in reconfigurable modular avionics systems
… requirements drive a constant demand for the increase in system functionality and performance, improvements in availability, survivability and mission effectiveness whilst reducing aircrew workload and life cycle costs. The rapid development of integrated circuit design and fabrication …
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On fault coverage and fault simulation for multiple signature analysis BIST schemes
… related to multiple signature analysis (MSA) built-in self-test (BIST) schemes are treated here. A model to predict the fault coverage is presented. Based on this model, the nature of the fault coverage for MSA is discussed. The fault coverage of MSA is a function of both the signature sizes …
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A wideband frequency synthesizer for built-in self testing of analog integrated circuits
The cost to test chips has risen tremendously. Additionally, the process for testing all functionalities of both analog and digital part is far from simple. One attractive option is moving some or all of the testing functions onto the chip itself leading to the use of built-in self-tests (BISTs). …
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Merging concurrent checking and off-line BIST
… dissertation encompasses primarily design for testability (DFT) problems of concurrent checking and structural off-line Built-In Self-Test. We present a new DFT method, which employs cyclic code checking as a medium to combine the concurrent checking and signature analysis in a built-in …
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In-System Testing of Configurable Logic Blocks in Xilinx 7-Series FPGAs
… recovery techniques, such as bitstream scrubbing, are only limited to detecting and correcting soft errors that corrupt the configuration memory. Scrubbing and related techniques cannot detect permanent faults within the FPGA fabric, such as short circuits and open circuits in FPGA transistors …
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Techniques for Enhancing Test and Diagnosis of Digital Circuits
Test and Diagnosis are critical areas in semiconductor manufacturing. Every chip manufactured using a new or premature technology or process needs to be tested for manufacturing defects to ensure defective chips are not sold to the customer. Conventionally, test is done by mounting the chip on an …
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Testing and Fault-Tolerance Aspects of High-Density VLSI Memory
Presented in this thesis is a design strategy for efficient and comprehensive parallel testing of both Random Access Memory (RAM) and Content Addressable Memory (CAM). Based on this design for testability approach, parallel testing algorithms for RAMs and CAMs are developed for a broad class of …
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The testability of regular logic structures
… logic structures has become very important in the recent past due to the complexity of the circuits that are being fabricated and the need to design, test and debug them. The testability of different classes of regular logic structures that are widely used in many practical applications is …
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High-Level Synthesis and Implementation of Built-In Self-Testable Data Path Intensive Circuit
A high-level built-in self-test (BIST) synthesis is a process of transforming a behavioral description into a register-transfer level structural description while minimizing BIST overhead. Existing high-level BIST synthesis methods focus on one objective, minimizing either area overhead or test …
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A Complete & Practical Approach to Ensure the Legality of a Signal Transmitted by a Cognitive Radio
… to create a cognitive radio are quickly becoming available. There are many advantages to having a radio operated by cognitive engine, and so cognitive radios are likely to become very popular in the future. One of the main difficulties associated with the cognitive radio is ensuring the signal …
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Novel methods for post-manufacturing and in-field testing of VLSI circuits/systems
In this work, at first we analyze and evaluate, the already known test data compression schemes for post-manufacturing testing and the DFT mechanisms for the enhancement of in-field testing and circuit reliability. We propose a new dictionary based test data compression method for …
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FIELD-PROGRAMMABLE MICROFLUIDIC TEST PLATFORM FOR POINT-OF-CARE DIAGNOSTICS
Early work in electrowetting on dielectric (EWOD) devices has demonstrated their great potential in microfluidics; however, further work is needed to integrate EWOD technology into a system deployable for point-of-care (POC) diagnostics. This research is aimed at providing enabling technologies …
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Low Power High Fault Coverage Test Techniques for Digital VLSI Circuits
Testing of digital VLSI circuits entails many challenges as a consequence of rapid growth of semiconductor manufacturing technology and the unprecedented levels of design complexity and the gigahertz range of operating frequencies. These challenges include keeping the average and peak power …
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