A SEIR-based ADC built-in-self-test and its application in ADC self-calibration

The static linearity test is one of the fundamental production tests used to measure DC performance of analog to digital converters (ADCs). It comes with high test equipment cost. An ADC built-in-self-test (BIST) is an attractive solution. However the stringent linearity requirement for an on-chip signal generator has made it prohibitive. The stimulus error identification and removal (SEIR) method has greatly reduced the linearity requirement. However, it requires a highly stable voltage offset, which remains a daunting task. This work exploits the inherit capacitive sample-and-hold circuit used in various ADC architectures to inject offset with very good constancy. A 16-bit successive approximate register (SAR) ADC with the proposed BIST scheme is modeled and simulated in Matlab to prove its validity. The results show that the estimation error on the maximum INL is less than 0.07 LSB. This BIST solution is then naturally extended to the calibration of an ADC. It is shown missing codes of such ADC can be effectively estimated and calibrated out.

Name thesis:degree_name

Master of Science in Engineering

Level thesis:degree_level

Masters

Discipline thesis:degree_discipline

Electrical and Computer Engineering

Grantor

The University of Texas at Austin

Year dc:date.issued

2013

Author dc:creator

• Jin, Xiankun

Advisor dc:contributor.advisor

• Sun, Nan

• ADC BIST
• SEIR
• Digital calibration
• SAR ADC
• Offset injection

Handle dc:identifier.uri

http://hdl.handle.net/2152/24051

OAI identifier oai:identifier

oai:repositories.lib.utexas.edu:2152/24051