{"id":{"repo_id":"texas","oai_identifier":"oai:repositories.lib.utexas.edu:2152/24051"},"canonical_url":"https://search.dev.ndltd.org/etd/texas/oai:repositories.lib.utexas.edu:2152/24051","repository":{"repo_id":"texas","name":"University of Texas","base_url":"https://repositories.lib.utexas.edu/server/oai/request"},"display":{"title":"A SEIR-based ADC built-in-self-test and its application in ADC self-calibration","abstract":"The static linearity test is one of the fundamental production tests used to measure DC performance of analog to digital converters (ADCs). It comes with high test equipment cost. An ADC built-in-self-test (BIST) is an attractive solution. However the stringent linearity requirement for an on-chip signal generator has made it prohibitive. The stimulus error identification and removal (SEIR) method has greatly reduced the linearity requirement. However, it requires a highly stable voltage offset, which remains a daunting task. This work exploits the inherit capacitive sample-and-hold circuit used in various ADC architectures to inject offset with very good constancy. A 16-bit successive approximate register (SAR) ADC with the proposed BIST scheme is modeled and simulated in Matlab to prove its validity. The results show that the estimation error on the maximum INL is less than 0.07 LSB. This BIST solution is then naturally extended to the calibration of an ADC. It is shown missing codes of such ADC can be effectively estimated and calibrated out.","abstract_html":"The static linearity test is one of the fundamental production tests used to measure DC performance of analog to digital converters (ADCs). It comes with high test equipment cost. An ADC built-in-self-test (BIST) is an attractive solution. However the stringent linearity requirement for an on-chip signal generator has made it prohibitive. The stimulus error identification and removal (SEIR) method has greatly reduced the linearity requirement. However, it requires a highly stable voltage offset, which remains a daunting task. This work exploits the inherit capacitive sample-and-hold circuit used in various ADC architectures to inject offset with very good constancy. A 16-bit successive approximate register (SAR) ADC with the proposed BIST scheme is modeled and simulated in Matlab to prove its validity. The results show that the estimation error on the maximum INL is less than 0.07 LSB. This BIST solution is then naturally extended to the calibration of an ADC. It is shown missing codes of such ADC can be effectively estimated and calibrated out.","abstract_has_math":false,"creators":["Jin, Xiankun"],"institution":"The University of Texas at Austin","degree_name":"Master of Science in Engineering","degree_level":"Masters","degree_discipline":"Electrical and Computer Engineering","degree_department":null,"school":null,"contributors":[],"advisors":["Sun, Nan"],"committee_chairs":[],"committee_members":[],"year":2013,"date_issued":"2013-12","date_published":"2013-12","updated_at":"2026-07-24T05:01:16Z","subjects":["ADC BIST","SEIR","Digital calibration","SAR ADC","Offset injection"],"languages":[],"rights":[],"rights_urls":[],"identifier_entries":[]},"links":{"outbound_url":"http://hdl.handle.net/2152/24051","outbound_label":"Handle","outbound_source":"dc:identifier.uri"},"metadata_groups":[{"id":"people","label":"People","entries":[{"key":"dc:contributor.advisor","label":"Advisor","values":["Sun, Nan"]},{"key":"dc:creator","label":"Author","values":["Jin, Xiankun"]}]},{"id":"academic_context","label":"Academic Context","entries":[{"key":"dc:date.accessioned","label":"Dc Date Accessioned","values":["2014-04-21T14:32:16Z"]},{"key":"dc:date.issued","label":"Date","values":["2013-12"]},{"key":"dc:type","label":"Dc Type","values":["Thesis"]},{"key":"thesis:degree_discipline","label":"Discipline","values":["Electrical and Computer Engineering"]},{"key":"thesis:degree_level","label":"Degree Level","values":["Masters"]},{"key":"thesis:degree_name","label":"Degree Name","values":["Master of Science in Engineering"]},{"key":"thesis:institution_name","label":"Thesis Institution Name","values":["The University of Texas at Austin"]}]},{"id":"subjects_keywords","label":"Subjects and Keywords","entries":[{"key":"dc:subject","label":"Dc Subject","values":["ADC BIST","SEIR","Digital calibration","SAR ADC","Offset injection"]}]},{"id":"identifiers","label":"Identifiers","entries":[{"key":"dc:identifier.uri","label":"Identifier URI","values":["http://hdl.handle.net/2152/24051"]}]},{"id":"additional","label":"Additional Metadata","entries":[{"key":"dc:description","label":"Description","values":["text"]},{"key":"dc:description.abstract","label":"Abstract","values":["The static linearity test is one of the fundamental production tests used to measure DC performance of analog to digital converters (ADCs). It comes with high test equipment cost. An ADC built-in-self-test (BIST) is an attractive solution. However the stringent linearity requirement for an on-chip signal generator has made it prohibitive. The stimulus error identification and removal (SEIR) method has greatly reduced the linearity requirement. However, it requires a highly stable voltage offset, which remains a daunting task. This work exploits the inherit capacitive sample-and-hold circuit used in various ADC architectures to inject offset with very good constancy. A 16-bit successive approximate register (SAR) ADC with the proposed BIST scheme is modeled and simulated in Matlab to prove its validity. The results show that the estimation error on the maximum INL is less than 0.07 LSB. This BIST solution is then naturally extended to the calibration of an ADC. It is shown missing codes of such ADC can be effectively estimated and calibrated out."]},{"key":"dc:format.mimetype","label":"Dc Format Mimetype","values":["application/pdf"]},{"key":"dc:title","label":"Title","values":["A SEIR-based ADC built-in-self-test and its application in ADC self-calibration"]}]}],"canonical_facts":{"dc:contributor.advisor":["Sun, Nan"],"dc:creator":["Jin, Xiankun"],"dc:date.accessioned":["2014-04-21T14:32:16Z"],"dc:date.issued":["2013-12"],"dc:description":["text"],"dc:description.abstract":["The static linearity test is one of the fundamental production tests used to measure DC performance of analog to digital converters (ADCs). It comes with high test equipment cost. An ADC built-in-self-test (BIST) is an attractive solution. However the stringent linearity requirement for an on-chip signal generator has made it prohibitive. The stimulus error identification and removal (SEIR) method has greatly reduced the linearity requirement. However, it requires a highly stable voltage offset, which remains a daunting task. This work exploits the inherit capacitive sample-and-hold circuit used in various ADC architectures to inject offset with very good constancy. A 16-bit successive approximate register (SAR) ADC with the proposed BIST scheme is modeled and simulated in Matlab to prove its validity. The results show that the estimation error on the maximum INL is less than 0.07 LSB. This BIST solution is then naturally extended to the calibration of an ADC. It is shown missing codes of such ADC can be effectively estimated and calibrated out."],"dc:format.mimetype":["application/pdf"],"dc:identifier.uri":["http://hdl.handle.net/2152/24051"],"dc:subject":["ADC BIST","SEIR","Digital calibration","SAR ADC","Offset injection"],"dc:title":["A SEIR-based ADC built-in-self-test and its application in ADC self-calibration"],"dc:type":["Thesis"],"thesis:degree_discipline":["Electrical and Computer Engineering"],"thesis:degree_level":["Masters"],"thesis:degree_name":["Master of Science in Engineering"],"thesis:institution_name":["The University of Texas at Austin"]},"updated_at":"2026-07-24T05:01:16Z"}