{"id":{"repo_id":"uiuc","oai_identifier":"oai:www.ideals.illinois.edu:2142/21902"},"canonical_url":"https://search.dev.ndltd.org/etd/uiuc/oai:www.ideals.illinois.edu:2142/21902","repository":{"repo_id":"uiuc","name":"University of Illinois - Urbana-Champaign","base_url":"https://www.ideals.illinois.edu/oai-pmh"},"display":{"title":"The testability of regular logic structures","abstract":"The use of regular logic structures has become very important in the recent past due to the complexity of the circuits that are being fabricated and the need to design, test and debug them. The testability of different classes of regular logic structures that are widely used in many practical applications is investigated in this thesis. The first class of circuits that is considered is called generalized counters. These are complex tree-structured circuits and can be represented by recursive mathematical equations. They do not possess rigid topological regularity. The testability of these circuits is investigated under the assumption of single as well as multiple faulty cells. A circuit design methodology is proposed that results in easily testable circuits when single faulty cells are assumed to occur. The second class of circuits examined is that of iterative logic arrays which are widely used in computer arithmetic hardware. The issues of design-for-testability, built-in self-test as well as automatic test generation for these circuits are discussed. The techniques developed are far more powerful and general than those conceived by previous researchers. A test generation program for iterative logic arrays that is the first of its kind to be written is discussed. The test generation problem for one-dimensional sequential arrays of cells is also analyzed. Such arrays, called bit-serial arrays, are widely used in many digital signal processing applications.","abstract_html":"The use of regular logic structures has become very important in the recent past due to the complexity of the circuits that are being fabricated and the need to design, test and debug them. The testability of different classes of regular logic structures that are widely used in many practical applications is investigated in this thesis. The first class of circuits that is considered is called generalized counters. These are complex tree-structured circuits and can be represented by recursive mathematical equations. They do not possess rigid topological regularity. The testability of these circuits is investigated under the assumption of single as well as multiple faulty cells. A circuit design methodology is proposed that results in easily testable circuits when single faulty cells are assumed to occur. The second class of circuits examined is that of iterative logic arrays which are widely used in computer arithmetic hardware. The issues of design-for-testability, built-in self-test as well as automatic test generation for these circuits are discussed. The techniques developed are far more powerful and general than those conceived by previous researchers. A test generation program for iterative logic arrays that is the first of its kind to be written is discussed. The test generation problem for one-dimensional sequential arrays of cells is also analyzed. Such arrays, called bit-serial arrays, are widely used in many digital signal processing applications.","abstract_has_math":false,"creators":["Chatterjee, Abhijit"],"institution":"University of Illinois at Urbana-Champaign","degree_name":"Ph.D.","degree_level":"Dissertation","degree_discipline":"Electrical Engineering","degree_department":null,"school":null,"contributors":["Abraham, Jacob A."],"advisors":[],"committee_chairs":[],"committee_members":[],"year":2011,"date_issued":"2011-05-07T13:22:42Z","date_published":"2011-05-07T13:22:42Z","updated_at":"2026-07-22T22:25:18Z","subjects":["Engineering, Electronics and Electrical","Computer Science"],"languages":["eng"],"rights":["Copyright 1990 Chatterjee, Abhijit"],"rights_urls":[],"identifier_entries":[{"key":"dc:identifier","label":"Identifier","values":["AAI9021660","(UMI)AAI9021660"],"render_values":[{"text":"AAI9021660","href":null,"code":true},{"text":"(UMI)AAI9021660","href":null,"code":true}]}]},"links":{"outbound_url":"http://hdl.handle.net/2142/21902","outbound_label":"Handle","outbound_source":"dc:identifier"},"metadata_groups":[{"id":"people","label":"People","entries":[{"key":"dc:contributor","label":"Contributor","values":["Abraham, Jacob A."]},{"key":"dc:creator","label":"Author","values":["Chatterjee, Abhijit"]}]},{"id":"academic_context","label":"Academic Context","entries":[{"key":"dc:date","label":"Dc Date","values":["2011-05-07T13:22:42Z","10000-01-01","1990"]},{"key":"dc:type","label":"Dc Type","values":["text"]},{"key":"thesis:degree_discipline","label":"Discipline","values":["Electrical Engineering"]},{"key":"thesis:degree_level","label":"Degree Level","values":["Dissertation"]},{"key":"thesis:degree_name","label":"Degree Name","values":["Ph.D."]},{"key":"thesis:institution_name","label":"Thesis Institution Name","values":["University of Illinois at Urbana-Champaign"]}]},{"id":"subjects_keywords","label":"Subjects and Keywords","entries":[{"key":"dc:subject","label":"Dc Subject","values":["Engineering, Electronics and Electrical","Computer Science"]}]},{"id":"language_rights","label":"Language and Rights","entries":[{"key":"dc:language","label":"Dc Language","values":["eng"]},{"key":"dc:rights","label":"Dc Rights","values":["Copyright 1990 Chatterjee, Abhijit"]}]},{"id":"identifiers","label":"Identifiers","entries":[{"key":"dc:identifier","label":"Identifier","values":["AAI9021660","(UMI)AAI9021660","http://hdl.handle.net/2142/21902"]}]},{"id":"additional","label":"Additional Metadata","entries":[{"key":"dc:description","label":"Description","values":["The use of regular logic structures has become very important in the recent past due to the complexity of the circuits that are being fabricated and the need to design, test and debug them. The testability of different classes of regular logic structures that are widely used in many practical applications is investigated in this thesis. The first class of circuits that is considered is called generalized counters. These are complex tree-structured circuits and can be represented by recursive mathematical equations. They do not possess rigid topological regularity. The testability of these circuits is investigated under the assumption of single as well as multiple faulty cells. A circuit design methodology is proposed that results in easily testable circuits when single faulty cells are assumed to occur. The second class of circuits examined is that of iterative logic arrays which are widely used in computer arithmetic hardware. The issues of design-for-testability, built-in self-test as well as automatic test generation for these circuits are discussed. The techniques developed are far more powerful and general than those conceived by previous researchers. A test generation program for iterative logic arrays that is the first of its kind to be written is discussed. The test generation problem for one-dimensional sequential arrays of cells is also analyzed. Such arrays, called bit-serial arrays, are widely used in many digital signal processing applications.","Made available in DSpace on 2011-05-07T13:22:42Z (GMT). No. of bitstreams: 2 license.txt: 4922 bytes, checksum: 910b249b4beec47e7ab768910c8f966f (MD5) 9021660.pdf: 10352757 bytes, checksum: 74174dd4675a6813d57291bcf5d462cc (MD5) Previous issue date: 1990","Item marked as restricted to the 'UIUC Users [automated]' Group (id=2) by Howard Ding (hding2@illinois.edu) on 2011-05-07T14:53:58Z Item is restricted indefinitely.","Restriction data tranferred 2014-07-01T11:25:01-05:00 Original Data Group with Access UIUC Users [automated] Release Date: none Reason: ETDs are only available to UIUC Users without author permission","ETDs are only available to UIUC Users without author permission","U of I Only"]},{"key":"dc:title","label":"Title","values":["The testability of regular logic structures"]}]}],"canonical_facts":{"dc:contributor":["Abraham, Jacob A."],"dc:creator":["Chatterjee, Abhijit"],"dc:date":["2011-05-07T13:22:42Z","10000-01-01","1990"],"dc:description":["The use of regular logic structures has become very important in the recent past due to the complexity of the circuits that are being fabricated and the need to design, test and debug them. The testability of different classes of regular logic structures that are widely used in many practical applications is investigated in this thesis. The first class of circuits that is considered is called generalized counters. These are complex tree-structured circuits and can be represented by recursive mathematical equations. They do not possess rigid topological regularity. The testability of these circuits is investigated under the assumption of single as well as multiple faulty cells. A circuit design methodology is proposed that results in easily testable circuits when single faulty cells are assumed to occur. The second class of circuits examined is that of iterative logic arrays which are widely used in computer arithmetic hardware. The issues of design-for-testability, built-in self-test as well as automatic test generation for these circuits are discussed. The techniques developed are far more powerful and general than those conceived by previous researchers. A test generation program for iterative logic arrays that is the first of its kind to be written is discussed. The test generation problem for one-dimensional sequential arrays of cells is also analyzed. Such arrays, called bit-serial arrays, are widely used in many digital signal processing applications.","Made available in DSpace on 2011-05-07T13:22:42Z (GMT). No. of bitstreams: 2 license.txt: 4922 bytes, checksum: 910b249b4beec47e7ab768910c8f966f (MD5) 9021660.pdf: 10352757 bytes, checksum: 74174dd4675a6813d57291bcf5d462cc (MD5) Previous issue date: 1990","Item marked as restricted to the 'UIUC Users [automated]' Group (id=2) by Howard Ding (hding2@illinois.edu) on 2011-05-07T14:53:58Z Item is restricted indefinitely.","Restriction data tranferred 2014-07-01T11:25:01-05:00 Original Data Group with Access UIUC Users [automated] Release Date: none Reason: ETDs are only available to UIUC Users without author permission","ETDs are only available to UIUC Users without author permission","U of I Only"],"dc:identifier":["AAI9021660","(UMI)AAI9021660","http://hdl.handle.net/2142/21902"],"dc:language":["eng"],"dc:rights":["Copyright 1990 Chatterjee, Abhijit"],"dc:subject":["Engineering, Electronics and Electrical","Computer Science"],"dc:title":["The testability of regular logic structures"],"dc:type":["text"],"thesis:degree_discipline":["Electrical Engineering"],"thesis:degree_level":["Dissertation"],"thesis:degree_name":["Ph.D."],"thesis:institution_name":["University of Illinois at Urbana-Champaign"]},"updated_at":"2026-07-22T22:25:18Z"}