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University of Illinois at Urbana-Champaign
A high-level approach to test generation for VLSI circuits
Abstract
dc:descriptionThe traditional approaches to test generation made use of the gate level representation of the circuit. This test generation problem is known to be NP-Complete for combinational circuits. A high level test generation approach has been designed on the basis of the branch and bound search procedure. This approach contains a data path test generator and a control circuit test generator.
Degree
thesis:*- Name thesis:degree_name
- Ph.D.
- Level thesis:degree_level
- Dissertation
- Discipline thesis:degree_discipline
- Electrical Engineering
- Grantor
- University of Illinois at Urbana-Champaign
- Year dc:date
- 2011
Author and committee
dc:creator, dc:contributor.*- Author dc:creator
-
- Narain, Prakash
- Contributors dc:contributor
-
- Patel, Janak H.
Subjects
dc:subject × 1Rights
dc:rights- Statement dc:rights
-
- Copyright 1992 Narain, Prakash
- Language dc:language
- eng
Identifiers
dc:identifier.*- Identifier
-
AAI9236550
(UMI)AAI9236550 - OAI identifier oai:identifier
- oai:www.ideals.illinois.edu:2142/21690