Global ETD Search
Search theses and dissertations gathered from participating repositories worldwide. Every result links back to the library that holds it. No account is needed.
Results
Showing 1 to 20 of 45 for “"Data Path"”.
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An automated method for data path construction
Thesis (M. Eng.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science; and, Thesis (B.S.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 1998.
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On low power floating point data path architectures
… design partition also allows simplification of data paths, so that the speed performance of these units are enhanced. With transition activity scaling, the switching activity of the floating point units is mapped to a limited subset of the hardware real estate, so that the time averaged power …
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A data path for a pixel-parallel image processing system
Thesis (M. Eng.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 1996.
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High-Level Synthesis and Implementation of Built-In Self-Testable Data Path Intensive Circuit
… heuristic method. It partitions a given data flow graph into smaller regions based on control steps and applies the ILP to each region successively to reduce the processing time. To measure the performance of BIST accurately and to demonstrate the practicality of our BIST synthesis …
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The design and construction of a data path chip set for a fault tolerant parallel processor
Thesis (M.S.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 1991.
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The Design, Simulation and Synthesis of Pipelined Floating-Point Radix-4 Fast Fourier Transform Data Path in VHDL
The Fast Fourier Transform (FFT) converts time or spatial information into the frequency domain. The FFT is one of the most widely used digital signal processing (DSP) algorithms. DSPs are used in a number of applications from communication and controls to speech and image processing. DSPs have …
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On synthesis and optimization of floating point units
… performance, transition activity scaled, double data path floating point multiplier has been proposed and its validity is proved by comparing it to a single data path floating point multiplier. A transition activity scaled, triple data path floating point adder has been compared with a high …
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Scheduling and allocation problems in high-level synthesis
… we study (1) the problem of scheduling dataflow graphs with conditional branches; (2) the problem of utilizing multi-port memories in data path synthesis; (3) the problem of integrating the scheduling and allocation steps; and (4) the problem of data path synthesis for testability.
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A real-time 256 x 256 pixel parallel image processing system by Zubair Aman Talib.
… done to test and demonstrate the PPIP chip. A data-path and controller board are used in conjunction with a 2 x 2 array (four-chip) PPIP test board to process 128 x 128 pixel images. A revision of the PPIP chip has been tested and characterized. A compact printed-circuit board design utilizes a …
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Asynchrobatic logic for low-power VLSI design
… number of possible methods for designing complex data-path cells used in the adiabatic data-path. Asynchrobatic Logic is then introduced as a comparison between asynchronous and Asynchrobatic buffer chains, showing that for wide systems, it operates more efficiently. Two more-complex sub-systems …
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VLSI Implementation of a Run-time Reconfigurable Custom Computing Integrated Circuit
… performance, FPGAs are limited by their narrow data path and small computational density. The Colt integrated circuit has been designed from the start to be the computational processing element in an RTR platform. Colt is an RTR data-flow processor array with a course-grain architecture (16-bit …
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A high-level approach to test generation for VLSI circuits
… bound search procedure. This approach contains a data path test generator and a control circuit test generator.
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Efficient VLSI Implementation of Arithmetic Units and Logic Circuits
… circuits is required for better performance of a data path unit and therefore microprocessor or digital signal processor (DSP). Adders are basic building blocks of any processor or data path application. For the design of high performance processing units, high-speed adders with low power …
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The E-algorithm: an automatic test generation algorithm for hardware description languages
… A fault model has been developed that addresses data path faults, faults in control structures, and faults in functional operators. The E-algorithm is able to generate tests for all modeled fault types, and handles a wide variety of circuit types, including sequential circuits. The algorithm has …
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Improved Signal Integrity in IEEE 1149.1 Boundary Scan Designs
… devices. A practical study of the TDI-TDO scan data path has been conducted to show where problems may arise in relationship to a particular board topology and test system. This work points to differences between passing and failing scan path tests for problem characterization. Serial data flow …
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Optimizing directory-based cache coherence on the RAW architecture
… memory requests, by providing a high speed data-path to local memory. However, in multi-processor systems utilizing shared memory, cache coherence protocols are necessary to ensure sequential consistency. Of the multiple coherence protocols developed, the scalability of directory-based …
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Enhancing end-to-end quality of service provisioning in wireless ad hoc networks using service vectors
… to choose different service classes along its data path. This scheme enhances the user benefits from the network services and network resource utilization, while maintaining the simplicity and scalability of the current Differentiated Services (DiffServ) network architecture. This thesis …
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Essays on networks and social interaction
… first paper develops a model for a new kind of data, "path data," that represents the sequential decisions made by actors navigating social, geographic, and other kinds of networks. The model is validated in a benchmark test, then used to measure sectarian influences in the ways that Sunni and …
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VLSI Implementation of a Wormhole Runtime Reconfigurable Processor
… little overheads and is very much suited for data-path based computations with deep computational pipelines. Stallion, second in the generation of Wormhole runtime reconfigurable processors, demonstrates the efficacy of wormhole runtime reconfiguration. The work presented here deals with the …
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