Improved Signal Integrity in IEEE 1149.1 Boundary Scan Designs

<p>This work is an analysis of solutions to problems derived from inherent timing and signal integrity issues in the use and application of the IEEE 1149.1 Standard at the board level in conjunction with its test system. Setup or hold times violations may occur in a boundary scan chain using IEEE 1149.1 compliant devices. A practical study of the TDI-TDO scan data path has been conducted to show where problems may arise in relationship to a particular board topology and test system. This work points to differences between passing and failing scan path tests for problem characterization. Serial data flow is then analyzed and suitability is discussed. Within certain conditions, a solution is proposed. This work has been shown to work on the test system. Recommendations are made based on this experimental approach.</p>

Name thesis:degree_name

MS

Grantor dc:publisher

Brigham Young University - Provo

Author dc:creator

• Taboada, Efren De Jesus Rangel

• 1149.1
• signal integrity
• tck
• boundary scan
• layout
• printed circuit test
• Computer Sciences
• Construction Engineering and Management

Language dc:language

English

Repository record dc:identifier

https://scholarsarchive.byu.edu/etd/668

OAI identifier oai:identifier

oai:scholarsarchive.byu.edu:etd-1667