{"id":{"repo_id":"uiuc","oai_identifier":"oai:www.ideals.illinois.edu:2142/21690"},"canonical_url":"https://search.dev.ndltd.org/etd/uiuc/oai:www.ideals.illinois.edu:2142/21690","repository":{"repo_id":"uiuc","name":"University of Illinois - Urbana-Champaign","base_url":"https://www.ideals.illinois.edu/oai-pmh"},"display":{"title":"A high-level approach to test generation for VLSI circuits","abstract":"The traditional approaches to test generation made use of the gate level representation of the circuit. This test generation problem is known to be NP-Complete for combinational circuits. A high level test generation approach has been designed on the basis of the branch and bound search procedure. This approach contains a data path test generator and a control circuit test generator.","abstract_html":"The traditional approaches to test generation made use of the gate level representation of the circuit. This test generation problem is known to be NP-Complete for combinational circuits. A high level test generation approach has been designed on the basis of the branch and bound search procedure. This approach contains a data path test generator and a control circuit test generator.","abstract_has_math":false,"creators":["Narain, Prakash"],"institution":"University of Illinois at Urbana-Champaign","degree_name":"Ph.D.","degree_level":"Dissertation","degree_discipline":"Electrical Engineering","degree_department":null,"school":null,"contributors":["Patel, Janak H."],"advisors":[],"committee_chairs":[],"committee_members":[],"year":2011,"date_issued":"2011-05-07T13:16:15Z","date_published":"2011-05-07T13:16:15Z","updated_at":"2026-07-22T22:25:18Z","subjects":["Engineering, Electronics and Electrical"],"languages":["eng"],"rights":["Copyright 1992 Narain, Prakash"],"rights_urls":[],"identifier_entries":[{"key":"dc:identifier","label":"Identifier","values":["AAI9236550","(UMI)AAI9236550"],"render_values":[{"text":"AAI9236550","href":null,"code":true},{"text":"(UMI)AAI9236550","href":null,"code":true}]}]},"links":{"outbound_url":"http://hdl.handle.net/2142/21690","outbound_label":"Handle","outbound_source":"dc:identifier"},"metadata_groups":[{"id":"people","label":"People","entries":[{"key":"dc:contributor","label":"Contributor","values":["Patel, Janak H."]},{"key":"dc:creator","label":"Author","values":["Narain, Prakash"]}]},{"id":"academic_context","label":"Academic Context","entries":[{"key":"dc:date","label":"Dc Date","values":["2011-05-07T13:16:15Z","10000-01-01","1992"]},{"key":"dc:type","label":"Dc Type","values":["text"]},{"key":"thesis:degree_discipline","label":"Discipline","values":["Electrical Engineering"]},{"key":"thesis:degree_level","label":"Degree Level","values":["Dissertation"]},{"key":"thesis:degree_name","label":"Degree Name","values":["Ph.D."]},{"key":"thesis:institution_name","label":"Thesis Institution Name","values":["University of Illinois at Urbana-Champaign"]}]},{"id":"subjects_keywords","label":"Subjects and Keywords","entries":[{"key":"dc:subject","label":"Dc Subject","values":["Engineering, Electronics and Electrical"]}]},{"id":"language_rights","label":"Language and Rights","entries":[{"key":"dc:language","label":"Dc Language","values":["eng"]},{"key":"dc:rights","label":"Dc Rights","values":["Copyright 1992 Narain, Prakash"]}]},{"id":"identifiers","label":"Identifiers","entries":[{"key":"dc:identifier","label":"Identifier","values":["AAI9236550","(UMI)AAI9236550","http://hdl.handle.net/2142/21690"]}]},{"id":"additional","label":"Additional Metadata","entries":[{"key":"dc:description","label":"Description","values":["The traditional approaches to test generation made use of the gate level representation of the circuit. This test generation problem is known to be NP-Complete for combinational circuits. A high level test generation approach has been designed on the basis of the branch and bound search procedure. This approach contains a data path test generator and a control circuit test generator.","The data path is modeled using a data flow graph. The gate level test generation concepts of propagation, justification and implication have been extended to high level. A dependency directed backtracking scheme has been designed for the algorithm.","The control circuit for test generation is modeled as a gate level interconnection of primitives. The data path is modeled as a high level interconnection. A sequential circuit test generation algorithm has been designed based upon forward time processing. A novel concept of initialization inference has been introduced.","Both of the approaches have been demonstrated to be very effective.","Made available in DSpace on 2011-05-07T13:16:15Z (GMT). No. of bitstreams: 2 license.txt: 4922 bytes, checksum: 910b249b4beec47e7ab768910c8f966f (MD5) 9236550.pdf: 2221813 bytes, checksum: 60b1f7228955105ea18b93cf99b1fef2 (MD5) Previous issue date: 1992","Item marked as restricted to the 'UIUC Users [automated]' Group (id=2) by Howard Ding (hding2@illinois.edu) on 2011-05-07T14:52:33Z Item is restricted indefinitely.","Restriction data tranferred 2014-07-01T11:24:12-05:00 Original Data Group with Access UIUC Users [automated] Release Date: none Reason: ETDs are only available to UIUC Users without author permission","ETDs are only available to UIUC Users without author permission","U of I Only"]},{"key":"dc:title","label":"Title","values":["A high-level approach to test generation for VLSI circuits"]}]}],"canonical_facts":{"dc:contributor":["Patel, Janak H."],"dc:creator":["Narain, Prakash"],"dc:date":["2011-05-07T13:16:15Z","10000-01-01","1992"],"dc:description":["The traditional approaches to test generation made use of the gate level representation of the circuit. This test generation problem is known to be NP-Complete for combinational circuits. A high level test generation approach has been designed on the basis of the branch and bound search procedure. This approach contains a data path test generator and a control circuit test generator.","The data path is modeled using a data flow graph. The gate level test generation concepts of propagation, justification and implication have been extended to high level. A dependency directed backtracking scheme has been designed for the algorithm.","The control circuit for test generation is modeled as a gate level interconnection of primitives. The data path is modeled as a high level interconnection. A sequential circuit test generation algorithm has been designed based upon forward time processing. A novel concept of initialization inference has been introduced.","Both of the approaches have been demonstrated to be very effective.","Made available in DSpace on 2011-05-07T13:16:15Z (GMT). No. of bitstreams: 2 license.txt: 4922 bytes, checksum: 910b249b4beec47e7ab768910c8f966f (MD5) 9236550.pdf: 2221813 bytes, checksum: 60b1f7228955105ea18b93cf99b1fef2 (MD5) Previous issue date: 1992","Item marked as restricted to the 'UIUC Users [automated]' Group (id=2) by Howard Ding (hding2@illinois.edu) on 2011-05-07T14:52:33Z Item is restricted indefinitely.","Restriction data tranferred 2014-07-01T11:24:12-05:00 Original Data Group with Access UIUC Users [automated] Release Date: none Reason: ETDs are only available to UIUC Users without author permission","ETDs are only available to UIUC Users without author permission","U of I Only"],"dc:identifier":["AAI9236550","(UMI)AAI9236550","http://hdl.handle.net/2142/21690"],"dc:language":["eng"],"dc:rights":["Copyright 1992 Narain, Prakash"],"dc:subject":["Engineering, Electronics and Electrical"],"dc:title":["A high-level approach to test generation for VLSI circuits"],"dc:type":["text"],"thesis:degree_discipline":["Electrical Engineering"],"thesis:degree_level":["Dissertation"],"thesis:degree_name":["Ph.D."],"thesis:institution_name":["University of Illinois at Urbana-Champaign"]},"updated_at":"2026-07-22T22:25:18Z"}