Scheduling and allocation problems in high-level synthesis

Various aspects of the two major tasks in high-level synthesis, scheduling and allocation, are studied in this thesis. Specifically, we study (1) the problem of scheduling dataflow graphs with conditional branches; (2) the problem of utilizing multi-port memories in data path synthesis; (3) the problem of integrating the scheduling and allocation steps; and (4) the problem of data path synthesis for testability.

Name thesis:degree_name

Ph.D.

Level thesis:degree_level

Dissertation

Discipline thesis:degree_discipline

Computer Science

Grantor

University of Illinois at Urbana-Champaign

Year dc:date

2011

Author dc:creator

• Kim, Taewhan

Contributors dc:contributor

• Liu, C.L.

• Applied Mechanics
• Engineering, Electronics and Electrical
• Computer Science

Statement dc:rights

• Copyright 1993 Kim, Taewhan

Language dc:language

eng

Identifier

AAI9411672
(UMI)AAI9411672

OAI identifier oai:identifier

oai:www.ideals.illinois.edu:2142/20327