{"id":{"repo_id":"uiuc","oai_identifier":"oai:www.ideals.illinois.edu:2142/20327"},"canonical_url":"https://search.dev.ndltd.org/etd/uiuc/oai:www.ideals.illinois.edu:2142/20327","repository":{"repo_id":"uiuc","name":"University of Illinois - Urbana-Champaign","base_url":"https://www.ideals.illinois.edu/oai-pmh"},"display":{"title":"Scheduling and allocation problems in high-level synthesis","abstract":"Various aspects of the two major tasks in high-level synthesis, scheduling and allocation, are studied in this thesis. Specifically, we study (1) the problem of scheduling dataflow graphs with conditional branches; (2) the problem of utilizing multi-port memories in data path synthesis; (3) the problem of integrating the scheduling and allocation steps; and (4) the problem of data path synthesis for testability.","abstract_html":"Various aspects of the two major tasks in high-level synthesis, scheduling and allocation, are studied in this thesis. Specifically, we study (1) the problem of scheduling dataflow graphs with conditional branches; (2) the problem of utilizing multi-port memories in data path synthesis; (3) the problem of integrating the scheduling and allocation steps; and (4) the problem of data path synthesis for testability.","abstract_has_math":false,"creators":["Kim, Taewhan"],"institution":"University of Illinois at Urbana-Champaign","degree_name":"Ph.D.","degree_level":"Dissertation","degree_discipline":"Computer Science","degree_department":null,"school":null,"contributors":["Liu, C.L."],"advisors":[],"committee_chairs":[],"committee_members":[],"year":2011,"date_issued":"2011-05-07T12:36:05Z","date_published":"2011-05-07T12:36:05Z","updated_at":"2026-07-22T22:25:15Z","subjects":["Applied Mechanics","Engineering, Electronics and Electrical","Computer Science"],"languages":["eng"],"rights":["Copyright 1993 Kim, Taewhan"],"rights_urls":[],"identifier_entries":[{"key":"dc:identifier","label":"Identifier","values":["AAI9411672","(UMI)AAI9411672"],"render_values":[{"text":"AAI9411672","href":null,"code":true},{"text":"(UMI)AAI9411672","href":null,"code":true}]}]},"links":{"outbound_url":"http://hdl.handle.net/2142/20327","outbound_label":"Handle","outbound_source":"dc:identifier"},"metadata_groups":[{"id":"people","label":"People","entries":[{"key":"dc:contributor","label":"Contributor","values":["Liu, C.L."]},{"key":"dc:creator","label":"Author","values":["Kim, Taewhan"]}]},{"id":"academic_context","label":"Academic Context","entries":[{"key":"dc:date","label":"Dc Date","values":["2011-05-07T12:36:05Z","10000-01-01","1993"]},{"key":"dc:type","label":"Dc Type","values":["text"]},{"key":"thesis:degree_discipline","label":"Discipline","values":["Computer Science"]},{"key":"thesis:degree_level","label":"Degree Level","values":["Dissertation"]},{"key":"thesis:degree_name","label":"Degree Name","values":["Ph.D."]},{"key":"thesis:institution_name","label":"Thesis Institution Name","values":["University of Illinois at Urbana-Champaign"]}]},{"id":"subjects_keywords","label":"Subjects and Keywords","entries":[{"key":"dc:subject","label":"Dc Subject","values":["Applied Mechanics","Engineering, Electronics and Electrical","Computer Science"]}]},{"id":"language_rights","label":"Language and Rights","entries":[{"key":"dc:language","label":"Dc Language","values":["eng"]},{"key":"dc:rights","label":"Dc Rights","values":["Copyright 1993 Kim, Taewhan"]}]},{"id":"identifiers","label":"Identifiers","entries":[{"key":"dc:identifier","label":"Identifier","values":["AAI9411672","(UMI)AAI9411672","http://hdl.handle.net/2142/20327"]}]},{"id":"additional","label":"Additional Metadata","entries":[{"key":"dc:description","label":"Description","values":["Various aspects of the two major tasks in high-level synthesis, scheduling and allocation, are studied in this thesis. Specifically, we study (1) the problem of scheduling dataflow graphs with conditional branches; (2) the problem of utilizing multi-port memories in data path synthesis; (3) the problem of integrating the scheduling and allocation steps; and (4) the problem of data path synthesis for testability.","Made available in DSpace on 2011-05-07T12:36:05Z (GMT). No. of bitstreams: 2 license.txt: 4922 bytes, checksum: 910b249b4beec47e7ab768910c8f966f (MD5) 9411672.pdf: 6216591 bytes, checksum: d3b2d5b29196e5184da763db6d5ec869 (MD5) Previous issue date: 1993","Item marked as restricted to the 'UIUC Users [automated]' Group (id=2) by Howard Ding (hding2@illinois.edu) on 2011-05-07T14:43:09Z Item is restricted indefinitely.","Restriction data tranferred 2014-07-01T11:18:50-05:00 Original Data Group with Access UIUC Users [automated] Release Date: none Reason: ETDs are only available to UIUC Users without author permission","ETDs are only available to UIUC Users without author permission","U of I Only"]},{"key":"dc:title","label":"Title","values":["Scheduling and allocation problems in high-level synthesis"]}]}],"canonical_facts":{"dc:contributor":["Liu, C.L."],"dc:creator":["Kim, Taewhan"],"dc:date":["2011-05-07T12:36:05Z","10000-01-01","1993"],"dc:description":["Various aspects of the two major tasks in high-level synthesis, scheduling and allocation, are studied in this thesis. Specifically, we study (1) the problem of scheduling dataflow graphs with conditional branches; (2) the problem of utilizing multi-port memories in data path synthesis; (3) the problem of integrating the scheduling and allocation steps; and (4) the problem of data path synthesis for testability.","Made available in DSpace on 2011-05-07T12:36:05Z (GMT). No. of bitstreams: 2 license.txt: 4922 bytes, checksum: 910b249b4beec47e7ab768910c8f966f (MD5) 9411672.pdf: 6216591 bytes, checksum: d3b2d5b29196e5184da763db6d5ec869 (MD5) Previous issue date: 1993","Item marked as restricted to the 'UIUC Users [automated]' Group (id=2) by Howard Ding (hding2@illinois.edu) on 2011-05-07T14:43:09Z Item is restricted indefinitely.","Restriction data tranferred 2014-07-01T11:18:50-05:00 Original Data Group with Access UIUC Users [automated] Release Date: none Reason: ETDs are only available to UIUC Users without author permission","ETDs are only available to UIUC Users without author permission","U of I Only"],"dc:identifier":["AAI9411672","(UMI)AAI9411672","http://hdl.handle.net/2142/20327"],"dc:language":["eng"],"dc:rights":["Copyright 1993 Kim, Taewhan"],"dc:subject":["Applied Mechanics","Engineering, Electronics and Electrical","Computer Science"],"dc:title":["Scheduling and allocation problems in high-level synthesis"],"dc:type":["text"],"thesis:degree_discipline":["Computer Science"],"thesis:degree_level":["Dissertation"],"thesis:degree_name":["Ph.D."],"thesis:institution_name":["University of Illinois at Urbana-Champaign"]},"updated_at":"2026-07-22T22:25:15Z"}