Diagnostic test set evaluation and enhancement

Diagnosis is an important but difficult problem in the design and manufacturing of VLSI circuits. This thesis contributes to two important diagnosis topics, namely diagnostic fault simulation and diagnostic test pattern generation. First, a diagnostic fault simulator for stuck-at faults in sequential circuits that is both time and space efficient is described. The simulator represents indistinguishable classes of faults as memory efficient lists. Second, diagnostically equivalent fault pairs in combinational circuits are identified using test generation and structural knowledge. A connection between redundant faults and a specific class of diagnostically equivalent fault pairs is established. A method to modify a conventional test generator for diagnostic test generation is also presented. The method utilizes circuit netlist modification along with a forced value at a primary input in the modified circuit. Finally, a technique to reduce the computation effort for diagnostic test pattern generation in sequential circuits is presented. The technique identifies some states that are impossible to justify in three-valued logic. This is achieved by performing test generation on certain transformed circuits to identify state elements that cannot be set to a particular value in three-valued logic.

Name thesis:degree_name

Ph.D.

Level thesis:degree_level

Dissertation

Discipline thesis:degree_discipline

Computer Science

Grantor

University of Illinois at Urbana-Champaign

Year dc:date

2011

Author dc:creator

• Hartanto, Ismed D.S.

Contributors dc:contributor

• Fuchs, W. Kent

• Engineering, Electronics and Electrical
• Computer Science

Statement dc:rights

• Copyright 1996 Hartanto, Ismed D. S.

Language dc:language

eng

Identifier

9780591198911
AAI9712301
(UMI)AAI9712301

OAI identifier oai:identifier

oai:www.ideals.illinois.edu:2142/19430