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Showing 1 to 20 of 24 for “"Test Pattern Generation"”.
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Built-In Schemes for Test Pattern Generation and Fault Location
… Carbondale. TITLE: BUILT-IN SCHEMES FOR TEST PATTERN GENERATION AND FAULT LOCATION MAJOR PROFESSOR: Dr. D. Kagaris In this dissertation, we studied the areas of test pattern generation and fault location for detecting and diagnosing the faults in today's complex chips. In the first …
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Test Pattern Generation and Test Application Time Reduction Algorithms for VLSI Circuits
Embargo set by: Seth Robbins for item 83238 Lift date: Forever Reason: Restricted to the U of I community idenfinitely during batch ingest of legacy ETDs
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Fault simulation and test pattern generation for synchronous and asynchronous sequential circuits
… called HOPE and HOPE2, and an autolllatic test pattern generator (ATPG), called ATHENA, for synchronous and asynchronous sequential circuits. HOPE is a parallel fault simulator for synchronous sequential circuits. In HOPE, a packet of 32 faults is simulated in parallel. Several new …
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On the Computation of LFSR Characteristic Polynomials for One-Dimensional and Two-Dimensional Test Pattern Generation
Current methodologies for built-in test pattern generation usually employ a predetermined linear feedback shift register (LFSR) in order to generate or decompress deterministic test patterns. As a direct consequence, the test pattern computation and the fault coverage are constrained to the …
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PARALLEL DELAY FAULT GRADING HEURISTIC AND TESTING APPROACHES TO TROJAN IC DETECTION
… to scale to multiple GPGPUs. A post-silicon test pattern generation strategy to maximize the efficiency of broadside tests applied to a sequential design for a limited test budget is presented. Arguments are made for this approach for detecting embedded Trojan ICs in the next-state functions …
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Diagnostic test set evaluation and enhancement
… diagnostic fault simulation and diagnostic test pattern generation. First, a diagnostic fault simulator for stuck-at faults in sequential circuits that is both time and space efficient is described. The simulator represents indistinguishable classes of faults as memory efficient lists. …
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Symbolic methods for testing digital circuits
… Decision Diagrams (BDDs), in the field of testing both combinational and synchronous sequential digital circuits at gate level. <br>Both major topics, fault simulation and automated test pattern generation (ATPG), have been examined, among others, like build-in self-test, computing reset …
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Techniques for sequential circuit automatic test generation
Test pattern generation has progressed to a stage at which automatic test generation gives satisfactory fault coverage on almost any combinational circuit. However, the same is not true of sequential circuit test generation. While scan-based approaches can convert the sequential circuit into a …
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Gate-Oxide-Short Defect Analysis and Fault Modeling Based on FinFET's 3D Structure
… new challenges in achieving reliable device testing. With the emergence of new types of defects and dominance of others, accurate modeling of the defects and generation of reliable fault models are essential to create realistic set of test vectors to detect the defects.Automatic test pattern …
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COPING WITH DISCREPANCIES OF THE MANUFACTURED WEIGHTS IN THRESHOLD LOGIC GATES
… weight defects is proposed. Also an Automatic Test Pattern Generation (ATPG) tool has been implemented that uses the fault model to detect whether the circuit is malfunctioning due to such weight-related defects. A novel design methodology is presented in this work to design complex TLG …
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Static Learning for Problems in VLSI Test and Verification
… of electronic design automation (EDA) including: test-pattern-generation, logic and fault simulation, fault diagnosis, logic optimization, etc. While logic implications have assisted in solving several EDA problems, their usefulness has not been fully explored. We believe that logic implications …
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Search State Extensibility based Learning Framework for Model Checking and Test Generation
… intensive design verification and manufacturing test phases in the product life-cycle of a digital system. On the contrary, time-to-market constraints require faster verification and test phases; otherwise it may result in a buggy design or a defective product. This trend in the semiconductor …
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On Enhancing Deterministic Sequential ATPG
… of deterministic sequential circuit Automatic Test Patterns Generators (ATPG). Three techniques make use of information gathered during test generation to help identify more unjustifiable states with higher percentage of "don't care" value. An approach for reducing the search space of the ATPG …
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SYNTHESIS AND TESTING OF THRESHOLD LOGIC CIRCUITS
… This renewed the interest in synthesis and testing of circuits with threshold logic gates. Two important synthesis considerations of threshold logic circuits are addressed namely, threshold logic function identification and reducing the total number of threshold logic gates required to …
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Design for Testability Techniques to Optimize VLSI Test Cost
High test data volume and long test application time are two major concerns for testing scan based circuits. The Illinois Scan (ILS) architecture has been shown to be effective in addressing both these issues. The ILS achieves a high degree of test data compression thereby reducing both the test …
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ATPG and DFT Algorithms for Delay Fault Testing
… and increasing clock rate on chips, delay testing is becoming a necessity in industry to maintain test quality for speed-related failures. The purpose of delay testing is to verify that the circuit operates correctly at the rated speed. However, functional tests for delay defects are …
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Functional timing analysis of VLSI circuits containing complex gates
… account, one must exercise all possible input patterns. Obviously, this is not possible to accomplish due to the high complexity of current designs. To circumvent this problem, designers must rely on timing analysis. Timing analysis is an input-independent verification approach that models each …
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Exploring Temporal and Spatial Correlations on Circuit Variables for Enhancing Simulation-based Test Generation
… and size of current circuit designs have made testing and verification major bottlenecks in the design flow of VLSI (Very Large Scale Integrated) circuits. Statistics show that more than 70% of the design effort can be spent on functional verification and manufacturing testing. This percentage …
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Techniques for Enhancing Test and Diagnosis of Digital Circuits
Test and Diagnosis are critical areas in semiconductor manufacturing. Every chip manufactured using a new or premature technology or process needs to be tested for manufacturing defects to ensure defective chips are not sold to the customer. Conventionally, test is done by mounting the chip on an …
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Strategies for Performance and Quality Improvement of Hardware Verification and Synthesis Algorithms
… equivalence checking, model checking, Automatic Test Pattern Generation (ATPG), functional Bi-decomposition, and technology mapping need to keep pace with these challenges. In this thesis, we are concerned with improving the quality and performance of different EDA algorithms particularly in area …
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