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University of Illinois at Urbana-Champaign
Test Pattern Generation and Test Application Time Reduction Algorithms for VLSI Circuits
Abstract
dc:descriptionEmbargo set by: Seth Robbins for item 83238 Lift date: Forever Reason: Restricted to the U of I community idenfinitely during batch ingest of legacy ETDs
Degree
thesis:*- Name thesis:degree_name
- Ph.D.
- Level thesis:degree_level
- Dissertation
- Discipline thesis:degree_discipline
- Computer Science
- Grantor
- University of Illinois at Urbana-Champaign
- Year dc:date
- 2015
Author and committee
dc:creator, dc:contributor.*- Author dc:creator
-
- Hamzaoglu, Ilker
- Contributors dc:contributor
-
- Patel, Janak H.
Subjects
dc:subject × 1Rights
- Language dc:language
- eng
Identifiers
dc:identifier.*- Identifier
- (MiAaPQ)AAI9953037
- OAI identifier oai:identifier
- oai:www.ideals.illinois.edu:2142/81957