TRAPEDS address tracing and its application to multicomputer cache performance analysis

Trace-driven simulation is an important aid in performance analysis of computer systems. Capturing address traces to use in these simulations, however, is a difficult problem, particularly for parallel processor architectures. Even when trace capture methods are applicable to parallel processors, the amount of collected data typically grows with the number of processors, thus increasing I/O and tracer storage costs. This thesis presents a new technique called TRAPEDS which modifies executable code (at the assembly language level) to dynamically collect the address trace from both the user code and the operating system and analyzes this trace during the execution of the program. This method helps resolve the I/O and storage limitations and facilitates concurrent analysis of the address trace. Implementation of TRAPEDS on the Intel iPSC/2 hypercube multicomputer is described. A method for minimizing the effect of tracing on the processor interaction ion the iPSC/2 is also introduced.

Name thesis:degree_name

Ph.D.

Level thesis:degree_level

Dissertation

Discipline thesis:degree_discipline

Electrical Engineering

Grantor

University of Illinois at Urbana-Champaign

Year dc:date

2011

Author dc:creator

• Stunkel, Craig Brian

Contributors dc:contributor

• Fuchs, W. Kent

• Engineering, Electronics and Electrical
• Computer Science

Statement dc:rights

• Copyright 1990 Stunkel, Craig Brian

Language dc:language

eng

Identifier

AAI9026327
(UMI)AAI9026327

OAI identifier oai:identifier

oai:www.ideals.illinois.edu:2142/19059