Global ETD Search
Search theses and dissertations gathered from participating repositories worldwide. Every result links back to the library that holds it. No account is needed.
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Showing 1 to 20 of 40 for “"parallel processors"”.
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High performance histogramming on massively parallel processors
… a histogram is, essentially, the antithesis of parallel processing. Without the use of slow atomic operations or serial execution when contributing data to a histogram bin in an input-driven method, there would likely be inaccuracies in the resulting output. An output-driven method would …
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Performance Evaluation and Modeling Techniques for Parallel Processors
This thesis addresses the issue of application performance under real operational conditions. A technique is introduced which accurately models the behavior of an application in real workloads. The methodology can evaluate the performance of the application as well as predict the effects on …
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Thread scheduling mechanisms for multiple-context parallel processors
Thesis (Ph. D.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 1995.
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Visual tracking of highly articulated objects using massively parallel processors
Hand gesture recognition has the potential of simplifying human computer interactions. However, the human hand is a highly articulated object, capable of taking on many different appearances. In this work, we consider an analysis by synthesis approach to this difficult tracking problem. We attempt …
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An application of artificial intelligence methods to scheduling parallel processors
… develop a scheduling and sequencing system for parallel processors, subject to preference, sequencing, and buffer inventory constraints. Specifically, hierarchical planning and, constraint-directed search were used to develop prototype scheduling system for a case study problem. This research …
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Solving Large and Sparse Zero-One Programming Problems on Parallel Processors
Made available in DSpace on 2014-12-10T20:13:32Z (GMT). No. of bitstreams: 1 7219808.pdf: 3449139 bytes, checksum: 3a793be33d1e738b487166bdb552bd8f (MD5) Previous issue date: 1972
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Energy-efficient latency tolerance for 1000-core data parallel processors with decoupled strands
… latency tolerance technique for 1000-core data parallel processors. The approach focuses on developing instruction latency tolerance to improve performance for a single thread. The main idea behind the approach is to leverage the compiler to split the original thread into separate …
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Spectral element solution of the Navier-Stokes equations on high performance distributed-memory parallel processors
Thesis (Ph. D.)--Massachusetts Institute of Technology, Dept. of Mechanical Engineering, 1989.
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Investigation of mean flow and vertical vorticity in turbulent convection using spectral simulations on massively parallel processors
Direct numerical simulations of Rayleigh-Benard convection are performed at several values of Rayleigh number (Ra). The computational domain consists of a square-planform rectangular box with horizontal-to-vertical aspect ratio equal to four. This domain is periodic in the horizontal directions, …
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Compiler and run-time support for irregular computations
… regular compiler analysis for Massively Parallel Processors (MPP) with distributed address space fails because the communication can only be determined at run-time. However, in many of these applications the communication pattern repeats for every iteration. Therefore, equivalent …
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Shared Cache Organization for Multiple-Stream Computer Systems
… of shared two-level memory hierarchies for parallel-pipelined multiple instruction stream processors are studied. The multicopy of data problems are totally eliminated by sharing the caches. All memory modules are assumed to be identical and cache addresses are interleaved by sets. For a …
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Efficient Iterative Methods for Saddle Point Problems
… system, and can be implemented efficiently on parallel processors. Along with a scalable parallel implementation described in the thesis, the multilevel algorithm yields a competitive parallel preconditioned iterative method for the solution of these problems.
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Parallel Processing Techniques for the Simulation of MOS VLSI Circuits Using Waveform Relaxation
… the simulation of MOS circuits exhibit natural parallelism, arising from the intrinsic partitioning of the circuit into subcircuits which are solved separately during the iterative solution process. Investigated in this thesis is the extent to which the overall run time of a simulation can be …
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Mapping regular recursive algorithms to fine-grained processor arrays
… growth of VLSI technology, special-purpose parallel processors have become a promising approach in the quest for high performance. Fine-grained processor arrays have become popular as they are suitable for solving problems with a high degree of parallelism, and can be inexpensively built …
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TRAPEDS address tracing and its application to multicomputer cache performance analysis
… is a difficult problem, particularly for parallel processor architectures. Even when trace capture methods are applicable to parallel processors, the amount of collected data typically grows with the number of processors, thus increasing I/O and tracer storage costs. This thesis presents a …
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Multipass communication systems for tiled processor architectures
… communication systems utilize multiple sets of parallel baseband receiver functions to balance communication data rates and available computation capabilities. This is achieved by spatially pipelining baseband functions across parallel resources to perform multiple processing passes on the same …
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Industrial control via a state language implementation on the transputer architecture
… architecture allows the exploitation of parallel processors. The thesis work involves the development of a prototypical state language based programmable controller whose software is comprised of two parts, a control strategy development tool and the controller shell. The development tool …
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Use of parallel co-processors in high speed position regulation
… price range. The use of the two processes as parallel processors (at times synchronous processors, and at other times asynchronous processors) decreased the position regulation execution time to the point that the device met all three requirements needed. The parallel programming techniques …
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A VLSI array processor architecture for emulating resistive network filtering
… implementations of an all-transistor analogue parallel processor that emulates the functionality of a resistive network. The problems related to VLSI -implementations of parallel processors are the main concern of this thesis. These problems are first discussed and then to overcome these …
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