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Georgia Institute of Technology
Economic lot scheduling for multiple products on parallel processors
Abstract
Ph.D.
Degree
thesis:*- Department dc:contributor.department
- Industrial engineering
- Grantor dc:publisher
- Georgia Institute of Technology
- Year dc:date.issued
- 1981
Author and committee
dc:creator, dc:contributor.*- Author dc:creator
-
- Carreno, Jose Juan
- Advisor dc:contributor.advisor
-
- Johnson, Lynwood A.
Rights
dc:rights- Statement dc:rights
-
- Access restricted to authorized Georgia Tech users only.
Identifiers
dc:identifier.*- Handle dc:identifier.uri
- http://hdl.handle.net/1853/25481
- OAI identifier oai:identifier
- oai:repository.gatech.edu:1853/25481