Design and implementation of a floating point unit for rigel, a massively parallel accelerator

Scientific applications rely heavily on floating point data types. Floating point operations are complex and require complicated hardware that is both area and power intensive. The emergence of massively parallel architectures like Rigel creates new challenges and poses new questions with respect to floating point support. The massively parallel aspect of Rigel places great emphasis on area efficient, low power designs. At the same time, Rigel is a general purpose accelerator and must provide high performance for a wide class of applications. This thesis presents an analysis of various floating point unit (FPU) components with respect to Rigel, and attempts to present a candidate design of an FPU that balances performance, area, and power and is suitable for massively parallel architectures like Rigel.

Name thesis:degree_name

M.S.

Level thesis:degree_level

Thesis

Discipline thesis:degree_discipline

Electrical & Computer Engineering

Grantor

University of Illinois at Urbana-Champaign

Year dc:date

2010

Author dc:creator

• Truty, Wojciech J.

Contributors dc:contributor

• Patel, Sanjay J.

• Floating point
• Rigel
• parallel
• many core
• multicore
• processor
• Accelerator
• Floating point unit (FPU)
• floating point unit
• IEEE Standard for Floating-Point Arithmetic (IEEE 754)
• Massively parallel

Statement dc:rights

• Copyright 2010 Wojciech Truty

Language dc:language

en

Handle dc:identifier

http://hdl.handle.net/2142/16472

OAI identifier oai:identifier

oai:www.ideals.illinois.edu:2142/16472