Global ETD Search
Search theses and dissertations gathered from participating repositories worldwide. Every result links back to the library that holds it. No account is needed.
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Showing 1 to 18 of 18 for “"Multicore processor"”.
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Migration from electronics to photonics in multicore processor
… of physical limits on interconnect. Microprocessor performance is now limited by the poor delay and bandwidth performance of the on - chip global wiring layer. This thesis is envisioned as a critical showstopper of electronic industry in the near future. The physical reason behind the …
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An FPGA implementation of multicore, multithreaded powerPC processors with memory subsystem using Bluespec
… the design, construction and integration of a multicore processor and a memory subsystem. The work is part of a joint project with IBM Watson research. The processors have multithreading capacities and implement the PowerPC ISA. The memory system consists of a parameterizable hierarchy of …
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Cycle-accurate modeling of multicore processors on FPGAs
… target design. We describe Arete, a full-system multicore processor simulator, developed using our modeling methodology. We provide details on Arete's resource-efficient and high-performance implementation on multiple FPGA platforms, and the architectural experiments performed using it. We …
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Load-balanced rendering on a general-purpose tiled architecture
… flexible graphics pipeline on Raw, a tile-based multicore processor. The complete graphics pipeline is expressed using StreamIt, a high-level language based on the stream programming model. The StreamIt compiler automatically maps the stream computation onto the Raw architecture. The system is …
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Energy scalability of on-chip interconnection networks
… buses form the communication backbone in multiprocessor systems-on-a-chip, multicore processors, and tiled processors. OCNs consume significant portions of a chip's energy budget, so their energy analysis early in the design cycle becomes important for architectural design decisions. Although …
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Smart scheduling : optimizing Tilera's process scheduling via reinforcement learning
As multicore processors become more prevalent, system complexities are increasing. It is no longer practical for an average programmer to balance all of the system constraints to ensure that the system will always perform optimally. One apparent solution to managing these resources efficiently is …
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Shared Memory Abstractions for Heterogeneous Multicore Processors
… diminishing returns from classic single-core processor designs, yet the number of transistors available for a processor is still increasing. Processor architects are therefore experimenting with a variety of multicore processor designs. Heterogeneous multicore processors with Explicitly …
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POWER-AWARE PERFORMANCE OPTIMIZATION ON MULTICORE ARCHITECTURES
… clock speed/operating frequency of mul- ticore processor to optimize the overall power consumption for a specific workload. Our work consists of four major parts. In the first part we propose a metric to determine core criticality. In multicore processing, certain threads/cores wait for other …
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Operating system level resource management for real-time systems
… In recent years, however, the emergence of multicore processor architecture and the growing number of battery powered devices make other aspects---such as contention in concurrently shared hardware resources and power consumption---also critical in providing required real-time performance. …
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dPool : a distributed data structure for factored operating systems
… parallelism through the addition of more processor cores. Architectural trends such as exponentially increasing parallelism and the possible lack of scalable shared memory motivate the reevaluation of operating system design. This thesis work takes place in the context of Factored …
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Vector support for multicore processors with major emphasis on configurable multiprocessors
… increasingly difficult to build higher speed uniprocessor chips because of performance degradation and high power consumption. The quadratically increasing circuit complexity forbade the exploration of more instruction-level parallelism (JLP). To continue raising the performance, processor …
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A Control-Theoretic Design And Analysis Framework For Resilient Hard Real-Time Systems
… the system resiliency of</p> <p>both uniprocessor and multicore processor systems.</p> <p>As a proof of concept, we first introduce a design metric called thermal-resiliency, which characterizes</p> <p>the maximum external thermal stress that any hard-real-time performance mode can …
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Locality-aware cache hierarchy management for multicore processors
Next generation multicore processors and applications will operate on massive data with significant sharing. A major challenge in their implementation is the storage requirement for tracking the sharers of data. The bit overhead for such storage scales quadratically with the number of cores in …
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Next-generation safety-critical systems using COTS based homogeneous multi-core processors and heterogeneous MPSoCS
… is pushing the transition from a single-core processor to a multicore processor where multiple single-core processors are packed into a single chip. With recent hardware advancements and the evolution of new challenging applications in autonomy such as self-driving cars and unmanned aerial …
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Instruction fusion and vector processor virtualization for higher throughput simultaneous multithreaded processors
… performance gains for new generation microprocessors. To alleviate its impact, an instruction fusion technique is first proposed for multiscalar and many-core processors. With instruction fusion, similar copies of an instruction to be run on multiple pipelines or cores are merged into a …
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Interconnect design techniques for multicore and 3D Integrated circuits.
… stringent power envelope. Over the last decade, multicore processors have emerged as a potential solution to address some of these problems by integrating multiple smaller and more energy efficient cores in order to replace a single, larger core. These cores must communicate through an efficient …
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Design and implementation of a floating point unit for rigel, a massively parallel accelerator
Scientific applications rely heavily on floating point data types. Floating point operations are complex and require complicated hardware that is both area and power intensive. The emergence of massively parallel architectures like Rigel creates new challenges and poses new questions with respect …
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Flexible memory protection for multicore processors
A system’s memory access control mechanisms profoundly impact the performance, reliability, security, and composability of the software it runs. Desirable features of an access control mechanism include: the ability to grant arbitrary permissions on any region of memory to any thread in the system; …