An FPGA implementation of multicore, multithreaded powerPC processors with memory subsystem using Bluespec

This thesis describes the design, construction and integration of a multicore processor and a memory subsystem. The work is part of a joint project with IBM Watson research. The processors have multithreading capacities and implement the PowerPC ISA. The memory system consists of a parameterizable hierarchy of caches and random access memory units. All implementation was done in Bluespec System Verilog hardware synthesis language for placement on FPGA. Furthermore, this document analyzes the main tradeoffs and major challenges involved in building and integrating such a system.

Department dc:contributor.department

Massachusetts Institute of Technology. Dept. of Electrical Engineering and Computer Science.

Grantor dc:publisher

Massachusetts Institute of Technology

Year dc:date.issued

2008

Author dc:creator

• Yamhure, Alessandro

Advisor dc:contributor.advisor

• Arvind.

• Electrical Engineering and Computer Science.

Statement dc:rights

• M.I.T. theses are protected by copyright. They may be viewed from this source for any purpose, but reproduction or distribution in any format is prohibited without written permission. See provided URL for inquiries about permission.

Licence dc:rights.uri

• http://dspace.mit.edu/handle/1721.1/7582

Language dc:language.iso

eng

Handle dc:identifier.uri

http://hdl.handle.net/1721.1/46534

OAI identifier oai:identifier

oai:dspace.mit.edu:1721.1/46534