Design of residue amplifiers for high-speed pipelined-SAR ADCs

This thesis presents the design of a high-speed Gm-R residue amplifier used in a pipelined-SAR ADC, implemented in a 28nm CMOS process. The proposed design achieves good linearity and low gain variation due to temperature using a constant-gm biasing network. The thesis is organized as follows: Chapter 1 introduces the concepts of ADCs and residue amplification. Chapter 2 discusses the backgrounds on architecture of the SAR ADC and pipelined-SAR ADC, and introduces residue amplifier design for pipelined-SAR ADC. Chapter 3 introduces the ADC architecture that is used with the Gm-R residue amplifier, design process and considerations of the Gm-R residue amplifier and layout. Chapter 4 shows the simulation results for the residue amplifier gain and nonlinearity, along with the ADC system level performances. Chapter 5 summarizes the findings and concludes the thesis.

Name thesis:degree_name

M.S.

Level thesis:degree_level

Thesis

Discipline thesis:degree_discipline

Electrical & Computer Engr

Grantor

University of Illinois Urbana-Champaign

Year dc:date

2025

Author dc:creator

• Liu, Shuozhen

Contributors dc:contributor

• Hanumolu, Pavan K.

• Analog-to-digital converter (ADC), Residue Amplifiers (RA), pipelined successive approximate register (SAR)

Statement dc:rights

• Copyright 2025 Shuozhen Liu

Language dc:language

en

Handle dc:identifier

https://hdl.handle.net/2142/132810

OAI identifier oai:identifier

oai:www.ideals.illinois.edu:2142/132810