{"id":{"repo_id":"uiuc","oai_identifier":"oai:www.ideals.illinois.edu:2142/132810"},"canonical_url":"https://search.dev.ndltd.org/etd/uiuc/oai:www.ideals.illinois.edu:2142/132810","repository":{"repo_id":"uiuc","name":"University of Illinois - Urbana-Champaign","base_url":"https://www.ideals.illinois.edu/oai-pmh"},"display":{"title":"Design of residue amplifiers for high-speed pipelined-SAR ADCs","abstract":"This thesis presents the design of a high-speed Gm-R residue amplifier used in a pipelined-SAR ADC, implemented in a 28nm CMOS process. The proposed design achieves good linearity and low gain variation due to temperature using a constant-gm biasing network. The thesis is organized as follows: Chapter 1 introduces the concepts of ADCs and residue amplification. Chapter 2 discusses the backgrounds on architecture of the SAR ADC and pipelined-SAR ADC, and introduces residue amplifier design for pipelined-SAR ADC. Chapter 3 introduces the ADC architecture that is used with the Gm-R residue amplifier, design process and considerations of the Gm-R residue amplifier and layout. Chapter 4 shows the simulation results for the residue amplifier gain and nonlinearity, along with the ADC system level performances. Chapter 5 summarizes the findings and concludes the thesis.","abstract_html":"This thesis presents the design of a high-speed Gm-R residue amplifier used in a pipelined-SAR ADC, implemented in a 28nm CMOS process. The proposed design achieves good linearity and low gain variation due to temperature using a constant-gm biasing network. The thesis is organized as follows: Chapter 1 introduces the concepts of ADCs and residue amplification. Chapter 2 discusses the backgrounds on architecture of the SAR ADC and pipelined-SAR ADC, and introduces residue amplifier design for pipelined-SAR ADC. Chapter 3 introduces the ADC architecture that is used with the Gm-R residue amplifier, design process and considerations of the Gm-R residue amplifier and layout. Chapter 4 shows the simulation results for the residue amplifier gain and nonlinearity, along with the ADC system level performances. Chapter 5 summarizes the findings and concludes the thesis.","abstract_has_math":false,"creators":["Liu, Shuozhen"],"institution":"University of Illinois Urbana-Champaign","degree_name":"M.S.","degree_level":"Thesis","degree_discipline":"Electrical & Computer Engr","degree_department":null,"school":null,"contributors":["Hanumolu, Pavan K."],"advisors":[],"committee_chairs":[],"committee_members":[],"year":2025,"date_issued":"2025-12","date_published":"2025-12","updated_at":"2026-07-22T22:25:07Z","subjects":["Analog-to-digital converter (ADC), Residue Amplifiers (RA), pipelined successive approximate register (SAR)"],"languages":["en"],"rights":["Copyright 2025 Shuozhen Liu"],"rights_urls":[],"identifier_entries":[]},"links":{"outbound_url":"https://hdl.handle.net/2142/132810","outbound_label":"Handle","outbound_source":"dc:identifier"},"metadata_groups":[{"id":"people","label":"People","entries":[{"key":"dc:contributor","label":"Contributor","values":["Hanumolu, Pavan K."]},{"key":"dc:creator","label":"Author","values":["Liu, Shuozhen"]}]},{"id":"academic_context","label":"Academic Context","entries":[{"key":"dc:date","label":"Dc Date","values":["2025-12","2025-12-12"]},{"key":"dc:type","label":"Dc Type","values":["text","Thesis"]},{"key":"thesis:degree_discipline","label":"Discipline","values":["Electrical & Computer Engr"]},{"key":"thesis:degree_level","label":"Degree Level","values":["Thesis"]},{"key":"thesis:degree_name","label":"Degree Name","values":["M.S."]},{"key":"thesis:institution_name","label":"Thesis Institution Name","values":["University of Illinois Urbana-Champaign"]}]},{"id":"subjects_keywords","label":"Subjects and Keywords","entries":[{"key":"dc:subject","label":"Dc Subject","values":["Analog-to-digital converter (ADC), Residue Amplifiers (RA), pipelined successive approximate register (SAR)"]}]},{"id":"language_rights","label":"Language and Rights","entries":[{"key":"dc:language","label":"Dc Language","values":["en"]},{"key":"dc:rights","label":"Dc Rights","values":["Copyright 2025 Shuozhen Liu"]}]},{"id":"identifiers","label":"Identifiers","entries":[{"key":"dc:identifier","label":"Identifier","values":["https://hdl.handle.net/2142/132810"]}]},{"id":"additional","label":"Additional Metadata","entries":[{"key":"dc:description","label":"Description","values":["This thesis presents the design of a high-speed Gm-R residue amplifier used in a pipelined-SAR ADC, implemented in a 28nm CMOS process. The proposed design achieves good linearity and low gain variation due to temperature using a constant-gm biasing network. The thesis is organized as follows: Chapter 1 introduces the concepts of ADCs and residue amplification. Chapter 2 discusses the backgrounds on architecture of the SAR ADC and pipelined-SAR ADC, and introduces residue amplifier design for pipelined-SAR ADC. Chapter 3 introduces the ADC architecture that is used with the Gm-R residue amplifier, design process and considerations of the Gm-R residue amplifier and layout. Chapter 4 shows the simulation results for the residue amplifier gain and nonlinearity, along with the ADC system level performances. Chapter 5 summarizes the findings and concludes the thesis.","Submission published under a 24 month embargo labeled 'Closed Access', the embargo will last until 2027-12-01","The student, Shuozhen Liu, accepted the attached license on 2025-12-11 at 12:41.","The student, Shuozhen Liu, submitted this Thesis for approval on 2025-12-11 at 12:55.","This Thesis was approved for publication on 2025-12-12 at 11:06.","DSpace SAF Submission Ingestion Package generated from Vireo submission #23119 on 2026-02-19 at 20:10:10"]},{"key":"dc:format","label":"Dc Format","values":["application/pdf"]},{"key":"dc:title","label":"Title","values":["Design of residue amplifiers for high-speed pipelined-SAR ADCs"]}]}],"canonical_facts":{"dc:contributor":["Hanumolu, Pavan K."],"dc:creator":["Liu, Shuozhen"],"dc:date":["2025-12","2025-12-12"],"dc:description":["This thesis presents the design of a high-speed Gm-R residue amplifier used in a pipelined-SAR ADC, implemented in a 28nm CMOS process. The proposed design achieves good linearity and low gain variation due to temperature using a constant-gm biasing network. The thesis is organized as follows: Chapter 1 introduces the concepts of ADCs and residue amplification. Chapter 2 discusses the backgrounds on architecture of the SAR ADC and pipelined-SAR ADC, and introduces residue amplifier design for pipelined-SAR ADC. Chapter 3 introduces the ADC architecture that is used with the Gm-R residue amplifier, design process and considerations of the Gm-R residue amplifier and layout. Chapter 4 shows the simulation results for the residue amplifier gain and nonlinearity, along with the ADC system level performances. Chapter 5 summarizes the findings and concludes the thesis.","Submission published under a 24 month embargo labeled 'Closed Access', the embargo will last until 2027-12-01","The student, Shuozhen Liu, accepted the attached license on 2025-12-11 at 12:41.","The student, Shuozhen Liu, submitted this Thesis for approval on 2025-12-11 at 12:55.","This Thesis was approved for publication on 2025-12-12 at 11:06.","DSpace SAF Submission Ingestion Package generated from Vireo submission #23119 on 2026-02-19 at 20:10:10"],"dc:format":["application/pdf"],"dc:identifier":["https://hdl.handle.net/2142/132810"],"dc:language":["en"],"dc:rights":["Copyright 2025 Shuozhen Liu"],"dc:subject":["Analog-to-digital converter (ADC), Residue Amplifiers (RA), pipelined successive approximate register (SAR)"],"dc:title":["Design of residue amplifiers for high-speed pipelined-SAR ADCs"],"dc:type":["text","Thesis"],"thesis:degree_discipline":["Electrical & Computer Engr"],"thesis:degree_level":["Thesis"],"thesis:degree_name":["M.S."],"thesis:institution_name":["University of Illinois Urbana-Champaign"]},"updated_at":"2026-07-22T22:25:07Z"}