A 1.7GS/s SAR ADC in 28nm CMOS

This thesis presents a 1.7GS/s 9b single channel SAR ADC in 28nm CMOS technology. The main focus of the thesis is the leveraging of the pipelining, passive residue transfer, and partial interleaving techniques to increase sample rate of the ADC. The first chapter explains the motivation for increasing the single channel ADC speed as well as the operation of the SAR ADC and pipelined SAR ADC and their inherent limitations. The second chapter presents the architecture investigated in this project. The third chapter details the circuit level implementation of the ADC. The fourth chapter shows simulation results, and the fifth chapter presents the conclusions.

Name thesis:degree_name

M.S.

Level thesis:degree_level

Thesis

Discipline thesis:degree_discipline

Electrical & Computer Engr

Grantor

University of Illinois Urbana-Champaign

Year dc:date

2025

Author dc:creator

• Burns, John Erick

Contributors dc:contributor

• Hanumolu, Pavan K

• SAR ADC
• Pipelined SAR ADC
• Passive residue transfer
• Partial interleaving

Statement dc:rights

• Copyright 2025 John Burns

Language dc:language

en

Handle dc:identifier

https://hdl.handle.net/2142/132607

OAI identifier oai:identifier

oai:www.ideals.illinois.edu:2142/132607