Design space exploration of binary algebraic hard decision decoders for data center connectivity

The recent adoption of large artificial intelligence models with trillions of parameters has introduced the need for new connectivity solutions. These complex models are trained within data centers, involving coordinated execution across thousands of compute nodes, which requires the connectivity between these compute sockets to support higher data rates with lower latency and energy costs. This justifies a need to re-evaluate current communication systems and design connectivity links capable of supporting the rapidly growing compute and energy consumption of these future workloads. Forward error correction is a key component in enabling high-throughput, low-latency, and energy-efficient communication links, reducing the need for costly protocol-level retransmission and relaxing the signal-to-noise ratio requirements on the channel and analog front-end circuits. However, the design space of forward error correction implementations is vast, spanning across diverse families of codes, each with their corresponding decoding algorithms and very large-scale integration architectures. In this thesis, we explore the design space of binary algebraic hard decision decoders for connectivity. We first analyze and derive specifications on FEC for short-reach connectivity. These stringent requirements indicate that published works and implementations from communication standards do not meet these requirements. Therefore, we hypothesize that algebraic hard decision decoders, under a modern process node, are suitable baselines for connectivity due to their efficient decoding algorithms and high-speed architectures. We justify this both information-theoretically and experimentally, using a design space exploration methodology with place-and-routed circuit data points in a 28 nm process. From this exploration, we find that these algebraic decoders meet the connectivity specifications quite comfortably, which validates our hypothesis and provides a strong baseline to design decoders for future workloads.

Name thesis:degree_name

M.S.

Level thesis:degree_level

Thesis

Discipline thesis:degree_discipline

Electrical & Computer Engr

Grantor

University of Illinois Urbana-Champaign

Year dc:date

2025

Author dc:creator

• Lee, Gene

Contributors dc:contributor

• Shanbhag, Naresh R.

• Forward Error Correction
• Vlsi
• Design Space Exploration
• Data Center Connectivity
• Algebraic Decoders

Statement dc:rights

• Copyright 2025 Gene Lee

Language dc:language

en, eng

Handle dc:identifier

https://hdl.handle.net/2142/130216

OAI record oai:identifier

https://www.ideals.illinois.edu/oai-pmh?verb=GetRecord&metadataPrefix=etdms&identifier=oai%3Awww.ideals.illinois.edu%3A2142%2F130216