{"id":{"repo_id":"uiuc","oai_identifier":"oai:www.ideals.illinois.edu:2142/130216"},"canonical_url":"https://search.dev.ndltd.org/etd/uiuc/oai:www.ideals.illinois.edu:2142/130216","repository":{"repo_id":"uiuc","name":"University of Illinois - Urbana-Champaign","base_url":"https://www.ideals.illinois.edu/oai-pmh"},"display":{"title":"Design space exploration of binary algebraic hard decision decoders for data center connectivity","abstract":"Submission published under a 24 month embargo labeled 'Closed Access', the embargo will last until 2027-08-01","abstract_html":"Submission published under a 24 month embargo labeled 'Closed Access', the embargo will last until 2027-08-01","abstract_has_math":false,"creators":["Lee, Gene"],"institution":"University of Illinois Urbana-Champaign","degree_name":"M.S.","degree_level":"Thesis","degree_discipline":"Electrical & Computer Engr","degree_department":null,"school":null,"contributors":["Shanbhag, Naresh R."],"advisors":[],"committee_chairs":[],"committee_members":[],"year":2025,"date_issued":"2025-07-24","date_published":"2025-07-24","updated_at":"2026-07-22T22:25:06Z","subjects":["Forward Error Correction","Vlsi","Design Space Exploration","Data Center Connectivity","Algebraic Decoders"],"languages":["en","eng"],"rights":["Copyright 2025 Gene Lee"],"rights_urls":[],"identifier_entries":[]},"links":{"outbound_url":"https://hdl.handle.net/2142/130216","outbound_label":"Handle","outbound_source":"dc:identifier"},"metadata_groups":[{"id":"people","label":"People","entries":[{"key":"dc:contributor","label":"Contributor","values":["Shanbhag, Naresh R."]},{"key":"dc:creator","label":"Author","values":["Lee, Gene"]}]},{"id":"academic_context","label":"Academic Context","entries":[{"key":"dc:date","label":"Dc Date","values":["2025-07-24","2025-08"]},{"key":"dc:type","label":"Dc Type","values":["text"]},{"key":"thesis:degree_discipline","label":"Discipline","values":["Electrical & Computer Engr"]},{"key":"thesis:degree_level","label":"Degree Level","values":["Thesis"]},{"key":"thesis:degree_name","label":"Degree Name","values":["M.S."]},{"key":"thesis:institution_name","label":"Thesis Institution Name","values":["University of Illinois Urbana-Champaign"]}]},{"id":"subjects_keywords","label":"Subjects and Keywords","entries":[{"key":"dc:subject","label":"Dc Subject","values":["Forward Error Correction","Vlsi","Design Space Exploration","Data Center Connectivity","Algebraic Decoders"]}]},{"id":"language_rights","label":"Language and Rights","entries":[{"key":"dc:language","label":"Dc Language","values":["en","eng"]},{"key":"dc:rights","label":"Dc Rights","values":["Copyright 2025 Gene Lee"]}]},{"id":"identifiers","label":"Identifiers","entries":[{"key":"dc:identifier","label":"Identifier","values":["https://hdl.handle.net/2142/130216"]}]},{"id":"additional","label":"Additional Metadata","entries":[{"key":"dc:description","label":"Description","values":["Submission published under a 24 month embargo labeled 'Closed Access', the embargo will last until 2027-08-01","The student, Gene Lee, accepted the attached license on 2025-07-24 at 12:17.","The student, Gene Lee, submitted this Thesis for approval on 2025-07-24 at 12:25.","This Thesis was approved for publication on 2025-07-24 at 13:09.","DSpace SAF Submission Ingestion Package generated from Vireo submission #22679 on 2025-10-25 at 15:54:24","The recent adoption of large artificial intelligence models with trillions of parameters has introduced the need for new connectivity solutions. These complex models are trained within data centers, involving coordinated execution across thousands of compute nodes, which requires the connectivity between these compute sockets to support higher data rates with lower latency and energy costs. This justifies a need to re-evaluate current communication systems and design connectivity links capable of supporting the rapidly growing compute and energy consumption of these future workloads. Forward error correction is a key component in enabling high-throughput, low-latency, and energy-efficient communication links, reducing the need for costly protocol-level retransmission and relaxing the signal-to-noise ratio requirements on the channel and analog front-end circuits. However, the design space of forward error correction implementations is vast, spanning across diverse families of codes, each with their corresponding decoding algorithms and very large-scale integration architectures. In this thesis, we explore the design space of binary algebraic hard decision decoders for connectivity. We first analyze and derive specifications on FEC for short-reach connectivity. These stringent requirements indicate that published works and implementations from communication standards do not meet these requirements. Therefore, we hypothesize that algebraic hard decision decoders, under a modern process node, are suitable baselines for connectivity due to their efficient decoding algorithms and high-speed architectures. We justify this both information-theoretically and experimentally, using a design space exploration methodology with place-and-routed circuit data points in a 28 nm process. From this exploration, we find that these algebraic decoders meet the connectivity specifications quite comfortably, which validates our hypothesis and provides a strong baseline to design decoders for future workloads."]},{"key":"dc:format","label":"Dc Format","values":["application/pdf"]},{"key":"dc:title","label":"Title","values":["Design space exploration of binary algebraic hard decision decoders for data center connectivity"]}]}],"canonical_facts":{"dc:contributor":["Shanbhag, Naresh R."],"dc:creator":["Lee, Gene"],"dc:date":["2025-07-24","2025-08"],"dc:description":["Submission published under a 24 month embargo labeled 'Closed Access', the embargo will last until 2027-08-01","The student, Gene Lee, accepted the attached license on 2025-07-24 at 12:17.","The student, Gene Lee, submitted this Thesis for approval on 2025-07-24 at 12:25.","This Thesis was approved for publication on 2025-07-24 at 13:09.","DSpace SAF Submission Ingestion Package generated from Vireo submission #22679 on 2025-10-25 at 15:54:24","The recent adoption of large artificial intelligence models with trillions of parameters has introduced the need for new connectivity solutions. These complex models are trained within data centers, involving coordinated execution across thousands of compute nodes, which requires the connectivity between these compute sockets to support higher data rates with lower latency and energy costs. This justifies a need to re-evaluate current communication systems and design connectivity links capable of supporting the rapidly growing compute and energy consumption of these future workloads. Forward error correction is a key component in enabling high-throughput, low-latency, and energy-efficient communication links, reducing the need for costly protocol-level retransmission and relaxing the signal-to-noise ratio requirements on the channel and analog front-end circuits. However, the design space of forward error correction implementations is vast, spanning across diverse families of codes, each with their corresponding decoding algorithms and very large-scale integration architectures. In this thesis, we explore the design space of binary algebraic hard decision decoders for connectivity. We first analyze and derive specifications on FEC for short-reach connectivity. These stringent requirements indicate that published works and implementations from communication standards do not meet these requirements. Therefore, we hypothesize that algebraic hard decision decoders, under a modern process node, are suitable baselines for connectivity due to their efficient decoding algorithms and high-speed architectures. We justify this both information-theoretically and experimentally, using a design space exploration methodology with place-and-routed circuit data points in a 28 nm process. From this exploration, we find that these algebraic decoders meet the connectivity specifications quite comfortably, which validates our hypothesis and provides a strong baseline to design decoders for future workloads."],"dc:format":["application/pdf"],"dc:identifier":["https://hdl.handle.net/2142/130216"],"dc:language":["en","eng"],"dc:rights":["Copyright 2025 Gene Lee"],"dc:subject":["Forward Error Correction","Vlsi","Design Space Exploration","Data Center Connectivity","Algebraic Decoders"],"dc:title":["Design space exploration of binary algebraic hard decision decoders for data center connectivity"],"dc:type":["text"],"thesis:degree_discipline":["Electrical & Computer Engr"],"thesis:degree_level":["Thesis"],"thesis:degree_name":["M.S."],"thesis:institution_name":["University of Illinois Urbana-Champaign"]},"updated_at":"2026-07-22T22:25:06Z"}