High-swing PAM4 electrical transmitter with clock data recovery based timing error correction

This thesis presents a high-swing PAM4 transmitter with an integrated CDR based timing calibration architecture implemented in a 16nm CMOS process. The proposed transmitter achieves a differential output swing of 2VDD using standard core devices. A CDR-based timing calibration circuit is introduced that detects timing errors at the transmitter output, allowing correction of all timing non-idealities throughout the signal path. Simulation results demon strate improved eye quality after calibration for PAM4 signaling.

Name thesis:degree_name

M.S.

Level thesis:degree_level

Thesis

Discipline thesis:degree_discipline

Electrical & Computer Engr

Grantor

University of Illinois Urbana-Champaign

Year dc:date

2025

Author dc:creator

• Shi, Ji

Contributors dc:contributor

• Hanumolu, Pavan Kumar

• High Speed Wireline Ic
• Clock Correction
• Serdes

Statement dc:rights

• Copyright 2025 Ji Shi

Language dc:language

en, eng

Handle dc:identifier

https://hdl.handle.net/2142/129780

OAI record oai:identifier

https://www.ideals.illinois.edu/oai-pmh?verb=GetRecord&metadataPrefix=etdms&identifier=oai%3Awww.ideals.illinois.edu%3A2142%2F129780