High-performance die-to-die interconnects

High-performance die-to-die interconnects play a critical role in enabling high-bandwidth, energy-efficient communication within multi-chip module architectures. This thesis explores the design and modeling of die-to-die interconnects, focusing on throughput enhancement techniques, energy-efficient circuit design, and advanced signaling schemes. The work begins with a cursory exploration of existing strategies to increase throughput such as increasing channel density, boosting per-lane data rates, and implementing multi-level signaling schemes such as PAM-4. A comprehensive modeling framework is developed to analyze link energy consumption, capturing the behavior of key components including serializers, deserializers, transmitters, receivers, and clock distribution networks. Relying on the results obtained from the modeling, architectural comparisons between NRZ and PAM-4 signaling show significant energy efficiency advantages for PAM-4 in ultra-high-speed applications. This thesis also presents the design and evaluation of a low-swing PAM-4 transmitter, validated through post-layout simulations in a 16nm FinFET process. Results demonstrate energy consumption of 160 fJ/bit at a data rate of 32 Gb/s, showcasing the transmitter’s feasibility for next-generation die-to-die interconnect systems. While this work establishes a robust foundation for interconnect design, future efforts could address more sophisticated channel modeling, advanced clock distribution techniques, and novel signaling schemes like simultaneous bidirectional signaling. These contributions will help advance the state-of-the-art in die-to-die interconnects, meeting the growing demands of scalable and energy-efficient computing architectures.

Name thesis:degree_name

M.S.

Level thesis:degree_level

Thesis

Discipline thesis:degree_discipline

Electrical & Computer Engr

Grantor

University of Illinois at Urbana-Champaign

Year dc:date

2024

Author dc:creator

• Patel, Sujay

Contributors dc:contributor

• Hanumolu, Pavan

• Die-to-die Interconnects
• Multi-chip Modules
• High-bandwidth Communication
• Serdes
• Pam-4
• Transmitter

Statement dc:rights

• Copyright 2024 Sujay Patel

Language dc:language

en, eng

Handle dc:identifier

https://hdl.handle.net/2142/127521

OAI record oai:identifier

https://www.ideals.illinois.edu/oai-pmh?verb=GetRecord&metadataPrefix=etdms&identifier=oai%3Awww.ideals.illinois.edu%3A2142%2F127521