{"id":{"repo_id":"uiuc","oai_identifier":"oai:www.ideals.illinois.edu:2142/127521"},"canonical_url":"https://search.dev.ndltd.org/etd/uiuc/oai:www.ideals.illinois.edu:2142/127521","repository":{"repo_id":"uiuc","name":"University of Illinois - Urbana-Champaign","base_url":"https://www.ideals.illinois.edu/oai-pmh"},"display":{"title":"High-performance die-to-die interconnects","abstract":"Submission published under a 24 month embargo labeled 'Closed Access', the embargo will last until 2026-12-01","abstract_html":"Submission published under a 24 month embargo labeled 'Closed Access', the embargo will last until 2026-12-01","abstract_has_math":false,"creators":["Patel, Sujay"],"institution":"University of Illinois at Urbana-Champaign","degree_name":"M.S.","degree_level":"Thesis","degree_discipline":"Electrical & Computer Engr","degree_department":null,"school":null,"contributors":["Hanumolu, Pavan"],"advisors":[],"committee_chairs":[],"committee_members":[],"year":2024,"date_issued":"2024-12-12","date_published":"2024-12-12","updated_at":"2026-07-22T22:25:04Z","subjects":["Die-to-die Interconnects","Multi-chip Modules","High-bandwidth Communication","Serdes","Pam-4","Transmitter"],"languages":["en","eng"],"rights":["Copyright 2024 Sujay Patel"],"rights_urls":[],"identifier_entries":[]},"links":{"outbound_url":"https://hdl.handle.net/2142/127521","outbound_label":"Handle","outbound_source":"dc:identifier"},"metadata_groups":[{"id":"people","label":"People","entries":[{"key":"dc:contributor","label":"Contributor","values":["Hanumolu, Pavan"]},{"key":"dc:creator","label":"Author","values":["Patel, Sujay"]}]},{"id":"academic_context","label":"Academic Context","entries":[{"key":"dc:date","label":"Dc Date","values":["2024-12-12","2024-12"]},{"key":"dc:type","label":"Dc Type","values":["text","Thesis"]},{"key":"thesis:degree_discipline","label":"Discipline","values":["Electrical & Computer Engr"]},{"key":"thesis:degree_level","label":"Degree Level","values":["Thesis"]},{"key":"thesis:degree_name","label":"Degree Name","values":["M.S."]},{"key":"thesis:institution_name","label":"Thesis Institution Name","values":["University of Illinois at Urbana-Champaign"]}]},{"id":"subjects_keywords","label":"Subjects and Keywords","entries":[{"key":"dc:subject","label":"Dc Subject","values":["Die-to-die Interconnects","Multi-chip Modules","High-bandwidth Communication","Serdes","Pam-4","Transmitter"]}]},{"id":"language_rights","label":"Language and Rights","entries":[{"key":"dc:language","label":"Dc Language","values":["en","eng"]},{"key":"dc:rights","label":"Dc Rights","values":["Copyright 2024 Sujay Patel"]}]},{"id":"identifiers","label":"Identifiers","entries":[{"key":"dc:identifier","label":"Identifier","values":["https://hdl.handle.net/2142/127521"]}]},{"id":"additional","label":"Additional Metadata","entries":[{"key":"dc:description","label":"Description","values":["Submission published under a 24 month embargo labeled 'Closed Access', the embargo will last until 2026-12-01","The student, Sujay Patel, accepted the attached license on 2024-12-12 at 14:32.","The student, Sujay Patel, submitted this Thesis for approval on 2024-12-12 at 14:37.","This Thesis was approved for publication on 2024-12-12 at 15:50.","DSpace SAF Submission Ingestion Package generated from Vireo submission #21585 on 2025-03-28 at 14:57:13","High-performance die-to-die interconnects play a critical role in enabling high-bandwidth, energy-efficient communication within multi-chip module architectures. This thesis explores the design and modeling of die-to-die interconnects, focusing on throughput enhancement techniques, energy-efficient circuit design, and advanced signaling schemes. The work begins with a cursory exploration of existing strategies to increase throughput such as increasing channel density, boosting per-lane data rates, and implementing multi-level signaling schemes such as PAM-4. A comprehensive modeling framework is developed to analyze link energy consumption, capturing the behavior of key components including serializers, deserializers, transmitters, receivers, and clock distribution networks. Relying on the results obtained from the modeling, architectural comparisons between NRZ and PAM-4 signaling show significant energy efficiency advantages for PAM-4 in ultra-high-speed applications. This thesis also presents the design and evaluation of a low-swing PAM-4 transmitter, validated through post-layout simulations in a 16nm FinFET process. Results demonstrate energy consumption of 160 fJ/bit at a data rate of 32 Gb/s, showcasing the transmitter’s feasibility for next-generation die-to-die interconnect systems. While this work establishes a robust foundation for interconnect design, future efforts could address more sophisticated channel modeling, advanced clock distribution techniques, and novel signaling schemes like simultaneous bidirectional signaling. These contributions will help advance the state-of-the-art in die-to-die interconnects, meeting the growing demands of scalable and energy-efficient computing architectures."]},{"key":"dc:format","label":"Dc Format","values":["application/pdf"]},{"key":"dc:title","label":"Title","values":["High-performance die-to-die interconnects"]}]}],"canonical_facts":{"dc:contributor":["Hanumolu, Pavan"],"dc:creator":["Patel, Sujay"],"dc:date":["2024-12-12","2024-12"],"dc:description":["Submission published under a 24 month embargo labeled 'Closed Access', the embargo will last until 2026-12-01","The student, Sujay Patel, accepted the attached license on 2024-12-12 at 14:32.","The student, Sujay Patel, submitted this Thesis for approval on 2024-12-12 at 14:37.","This Thesis was approved for publication on 2024-12-12 at 15:50.","DSpace SAF Submission Ingestion Package generated from Vireo submission #21585 on 2025-03-28 at 14:57:13","High-performance die-to-die interconnects play a critical role in enabling high-bandwidth, energy-efficient communication within multi-chip module architectures. This thesis explores the design and modeling of die-to-die interconnects, focusing on throughput enhancement techniques, energy-efficient circuit design, and advanced signaling schemes. The work begins with a cursory exploration of existing strategies to increase throughput such as increasing channel density, boosting per-lane data rates, and implementing multi-level signaling schemes such as PAM-4. A comprehensive modeling framework is developed to analyze link energy consumption, capturing the behavior of key components including serializers, deserializers, transmitters, receivers, and clock distribution networks. Relying on the results obtained from the modeling, architectural comparisons between NRZ and PAM-4 signaling show significant energy efficiency advantages for PAM-4 in ultra-high-speed applications. This thesis also presents the design and evaluation of a low-swing PAM-4 transmitter, validated through post-layout simulations in a 16nm FinFET process. Results demonstrate energy consumption of 160 fJ/bit at a data rate of 32 Gb/s, showcasing the transmitter’s feasibility for next-generation die-to-die interconnect systems. While this work establishes a robust foundation for interconnect design, future efforts could address more sophisticated channel modeling, advanced clock distribution techniques, and novel signaling schemes like simultaneous bidirectional signaling. These contributions will help advance the state-of-the-art in die-to-die interconnects, meeting the growing demands of scalable and energy-efficient computing architectures."],"dc:format":["application/pdf"],"dc:identifier":["https://hdl.handle.net/2142/127521"],"dc:language":["en","eng"],"dc:rights":["Copyright 2024 Sujay Patel"],"dc:subject":["Die-to-die Interconnects","Multi-chip Modules","High-bandwidth Communication","Serdes","Pam-4","Transmitter"],"dc:title":["High-performance die-to-die interconnects"],"dc:type":["text","Thesis"],"thesis:degree_discipline":["Electrical & Computer Engr"],"thesis:degree_level":["Thesis"],"thesis:degree_name":["M.S."],"thesis:institution_name":["University of Illinois at Urbana-Champaign"]},"updated_at":"2026-07-22T22:25:04Z"}