Power and signal delivery networks for heterogeneously integrated chiplets

It is increasingly challenging to satisfy the requirements placed on the power delivery network for a multilevel hierarchical system, due to aggressive voltage scaling and stringent limits on the chip-level voltage droop. This thesis presents a methodology to obtain the minimum number of decoupling capacitors for a 4-level hierarchical system to meet the on-chip voltage droop constraints and to optimize the location of those decoupling capacitors to meet a user-specified target impedance. The number and location optimizations are performed using nature-based and Bayesian optimization algorithms along with the quantitative comparison of results. This thesis also advances the current understanding and performance assessment of chiplet interfaces by providing a framework for modeling and simulation of signal and power integrity of Bunch-of-Wires (BoW) based die-to-die interconnects with advanced packaging technology. The study covers data rates up to 16 Gbps and includes a circuit-level implementation of the BoW slice consisting of a driver on one chiplet and a receiver on another chiplet. The width, spacing, and length of the high-density transmission lines are treated as variables in this work, and BoW data line configurations with extremely low power dissipation, less than 0.2 pJ/bit at 8 and 16 Gbps, are identified.

Name thesis:degree_name

M.S.

Level thesis:degree_level

Thesis

Discipline thesis:degree_discipline

Electrical & Computer Engr

Grantor

University of Illinois at Urbana-Champaign

Year dc:date

2024

Author dc:creator

• Krishna, Ram

Contributors dc:contributor

• Rosenbaum, Elyse

• Chiplet
• Pdn
• Bow

Statement dc:rights

• Copyright 2024 Ram Krishna

Language dc:language

en, eng

Handle dc:identifier

https://hdl.handle.net/2142/124532

OAI record oai:identifier

https://www.ideals.illinois.edu/oai-pmh?verb=GetRecord&metadataPrefix=etdms&identifier=oai%3Awww.ideals.illinois.edu%3A2142%2F124532