{"id":{"repo_id":"uiuc","oai_identifier":"oai:www.ideals.illinois.edu:2142/124532"},"canonical_url":"https://search.dev.ndltd.org/etd/uiuc/oai:www.ideals.illinois.edu:2142/124532","repository":{"repo_id":"uiuc","name":"University of Illinois - Urbana-Champaign","base_url":"https://www.ideals.illinois.edu/oai-pmh"},"display":{"title":"Power and signal delivery networks for heterogeneously integrated chiplets","abstract":"Submission published under a 24 month embargo labeled 'U of I Access', the embargo will last until 2026-05-01","abstract_html":"Submission published under a 24 month embargo labeled 'U of I Access', the embargo will last until 2026-05-01","abstract_has_math":false,"creators":["Krishna, Ram"],"institution":"University of Illinois at Urbana-Champaign","degree_name":"M.S.","degree_level":"Thesis","degree_discipline":"Electrical & Computer Engr","degree_department":null,"school":null,"contributors":["Rosenbaum, Elyse"],"advisors":[],"committee_chairs":[],"committee_members":[],"year":2024,"date_issued":"2024-05","date_published":"2024-05","updated_at":"2026-07-22T22:25:02Z","subjects":["Chiplet","Pdn","Bow"],"languages":["en","eng"],"rights":["Copyright 2024 Ram Krishna"],"rights_urls":[],"identifier_entries":[]},"links":{"outbound_url":"https://hdl.handle.net/2142/124532","outbound_label":"Handle","outbound_source":"dc:identifier"},"metadata_groups":[{"id":"people","label":"People","entries":[{"key":"dc:contributor","label":"Contributor","values":["Rosenbaum, Elyse"]},{"key":"dc:creator","label":"Author","values":["Krishna, Ram"]}]},{"id":"academic_context","label":"Academic Context","entries":[{"key":"dc:date","label":"Dc Date","values":["2024-05","2024-04-21"]},{"key":"dc:type","label":"Dc Type","values":["text"]},{"key":"thesis:degree_discipline","label":"Discipline","values":["Electrical & Computer Engr"]},{"key":"thesis:degree_level","label":"Degree Level","values":["Thesis"]},{"key":"thesis:degree_name","label":"Degree Name","values":["M.S."]},{"key":"thesis:institution_name","label":"Thesis Institution Name","values":["University of Illinois at Urbana-Champaign"]}]},{"id":"subjects_keywords","label":"Subjects and Keywords","entries":[{"key":"dc:subject","label":"Dc Subject","values":["Chiplet","Pdn","Bow"]}]},{"id":"language_rights","label":"Language and Rights","entries":[{"key":"dc:language","label":"Dc Language","values":["en","eng"]},{"key":"dc:rights","label":"Dc Rights","values":["Copyright 2024 Ram Krishna"]}]},{"id":"identifiers","label":"Identifiers","entries":[{"key":"dc:identifier","label":"Identifier","values":["https://hdl.handle.net/2142/124532"]}]},{"id":"additional","label":"Additional Metadata","entries":[{"key":"dc:description","label":"Description","values":["Submission published under a 24 month embargo labeled 'U of I Access', the embargo will last until 2026-05-01","The student, Ram Krishna, accepted the attached license on 2024-04-15 at 20:21.","The student, Ram Krishna, submitted this Thesis for approval on 2024-04-15 at 20:21.","This Thesis was approved for publication on 2024-04-21 at 17:19.","DSpace SAF Submission Ingestion Package generated from Vireo submission #20425 on 2024-09-16 at 00:43:44","It is increasingly challenging to satisfy the requirements placed on the power delivery network for a multilevel hierarchical system, due to aggressive voltage scaling and stringent limits on the chip-level voltage droop. This thesis presents a methodology to obtain the minimum number of decoupling capacitors for a 4-level hierarchical system to meet the on-chip voltage droop constraints and to optimize the location of those decoupling capacitors to meet a user-specified target impedance. The number and location optimizations are performed using nature-based and Bayesian optimization algorithms along with the quantitative comparison of results. This thesis also advances the current understanding and performance assessment of chiplet interfaces by providing a framework for modeling and simulation of signal and power integrity of Bunch-of-Wires (BoW) based die-to-die interconnects with advanced packaging technology. The study covers data rates up to 16 Gbps and includes a circuit-level implementation of the BoW slice consisting of a driver on one chiplet and a receiver on another chiplet. The width, spacing, and length of the high-density transmission lines are treated as variables in this work, and BoW data line configurations with extremely low power dissipation, less than 0.2 pJ/bit at 8 and 16 Gbps, are identified."]},{"key":"dc:format","label":"Dc Format","values":["application/pdf"]},{"key":"dc:title","label":"Title","values":["Power and signal delivery networks for heterogeneously integrated chiplets"]}]}],"canonical_facts":{"dc:contributor":["Rosenbaum, Elyse"],"dc:creator":["Krishna, Ram"],"dc:date":["2024-05","2024-04-21"],"dc:description":["Submission published under a 24 month embargo labeled 'U of I Access', the embargo will last until 2026-05-01","The student, Ram Krishna, accepted the attached license on 2024-04-15 at 20:21.","The student, Ram Krishna, submitted this Thesis for approval on 2024-04-15 at 20:21.","This Thesis was approved for publication on 2024-04-21 at 17:19.","DSpace SAF Submission Ingestion Package generated from Vireo submission #20425 on 2024-09-16 at 00:43:44","It is increasingly challenging to satisfy the requirements placed on the power delivery network for a multilevel hierarchical system, due to aggressive voltage scaling and stringent limits on the chip-level voltage droop. This thesis presents a methodology to obtain the minimum number of decoupling capacitors for a 4-level hierarchical system to meet the on-chip voltage droop constraints and to optimize the location of those decoupling capacitors to meet a user-specified target impedance. The number and location optimizations are performed using nature-based and Bayesian optimization algorithms along with the quantitative comparison of results. This thesis also advances the current understanding and performance assessment of chiplet interfaces by providing a framework for modeling and simulation of signal and power integrity of Bunch-of-Wires (BoW) based die-to-die interconnects with advanced packaging technology. The study covers data rates up to 16 Gbps and includes a circuit-level implementation of the BoW slice consisting of a driver on one chiplet and a receiver on another chiplet. The width, spacing, and length of the high-density transmission lines are treated as variables in this work, and BoW data line configurations with extremely low power dissipation, less than 0.2 pJ/bit at 8 and 16 Gbps, are identified."],"dc:format":["application/pdf"],"dc:identifier":["https://hdl.handle.net/2142/124532"],"dc:language":["en","eng"],"dc:rights":["Copyright 2024 Ram Krishna"],"dc:subject":["Chiplet","Pdn","Bow"],"dc:title":["Power and signal delivery networks for heterogeneously integrated chiplets"],"dc:type":["text"],"thesis:degree_discipline":["Electrical & Computer Engr"],"thesis:degree_level":["Thesis"],"thesis:degree_name":["M.S."],"thesis:institution_name":["University of Illinois at Urbana-Champaign"]},"updated_at":"2026-07-22T22:25:02Z"}