Heterogeneous CPU-FPGA system framework and scheduler

In this work, we explore two critical aspects of heterogeneous CPU-FPGA systems within high-performance computing: the optimization of single tasks and the effective scheduling of heavy workloads. We consider systems that consist of general-purpose units such as CPUs, and specialized accelerators, such as FPGAs, to boost computational efficiency and throughput. Our research centers on exploiting the multithreading of CPUs and the pipelined architecture of FPGAs. We specifically focus on the distribution of image processing tasks using the Canny edge detection algorithm as a representative test case to assess system performance under various workload conditions. Through a comprehensive series of experiments executed within the OpenCL framework, we assess the effectiveness of our task partitioning strategy alongside various task distribution methods between CPUs and FPGAs. These experiments are designed to explore the potential of integrating multi-thread CPUs with pipelined FPGAs to optimize the processing of multiple tasks. We also provide insights into the method of optimizing task allocation to minimize latency and maximize throughput, showcasing the potential of heterogeneous systems in handling computationally intensive applications efficiently.

Name thesis:degree_name

M.S.

Level thesis:degree_level

Thesis

Discipline thesis:degree_discipline

Electrical & Computer Engr

Grantor

University of Illinois at Urbana-Champaign

Year dc:date

2024

Author dc:creator

• Li, Luoyan

Contributors dc:contributor

• Kindratenko, Volodymyr

• Heterogeneous Computing
• Cpu+fpga
• Scheduler
• Opencl

Statement dc:rights

• Copyright 2024 Luoyan Li

Language dc:language

eng, en

Handle dc:identifier

https://hdl.handle.net/2142/124460

OAI identifier oai:identifier

oai:www.ideals.illinois.edu:2142/124460