{"id":{"repo_id":"uiuc","oai_identifier":"oai:www.ideals.illinois.edu:2142/124460"},"canonical_url":"https://search.dev.ndltd.org/etd/uiuc/oai:www.ideals.illinois.edu:2142/124460","repository":{"repo_id":"uiuc","name":"University of Illinois - Urbana-Champaign","base_url":"https://www.ideals.illinois.edu/oai-pmh"},"display":{"title":"Heterogeneous CPU-FPGA system framework and scheduler","abstract":"In this work, we explore two critical aspects of heterogeneous CPU-FPGA systems within high-performance computing: the optimization of single tasks and the effective scheduling of heavy workloads. We consider systems that consist of general-purpose units such as CPUs, and specialized accelerators, such as FPGAs, to boost computational efficiency and throughput. Our research centers on exploiting the multithreading of CPUs and the pipelined architecture of FPGAs. We specifically focus on the distribution of image processing tasks using the Canny edge detection algorithm as a representative test case to assess system performance under various workload conditions. Through a comprehensive series of experiments executed within the OpenCL framework, we assess the effectiveness of our task partitioning strategy alongside various task distribution methods between CPUs and FPGAs. These experiments are designed to explore the potential of integrating multi-thread CPUs with pipelined FPGAs to optimize the processing of multiple tasks. We also provide insights into the method of optimizing task allocation to minimize latency and maximize throughput, showcasing the potential of heterogeneous systems in handling computationally intensive applications efficiently.","abstract_html":"In this work, we explore two critical aspects of heterogeneous CPU-FPGA systems within high-performance computing: the optimization of single tasks and the effective scheduling of heavy workloads. We consider systems that consist of general-purpose units such as CPUs, and specialized accelerators, such as FPGAs, to boost computational efficiency and throughput. Our research centers on exploiting the multithreading of CPUs and the pipelined architecture of FPGAs. We specifically focus on the distribution of image processing tasks using the Canny edge detection algorithm as a representative test case to assess system performance under various workload conditions. Through a comprehensive series of experiments executed within the OpenCL framework, we assess the effectiveness of our task partitioning strategy alongside various task distribution methods between CPUs and FPGAs. These experiments are designed to explore the potential of integrating multi-thread CPUs with pipelined FPGAs to optimize the processing of multiple tasks. We also provide insights into the method of optimizing task allocation to minimize latency and maximize throughput, showcasing the potential of heterogeneous systems in handling computationally intensive applications efficiently.","abstract_has_math":false,"creators":["Li, Luoyan"],"institution":"University of Illinois at Urbana-Champaign","degree_name":"M.S.","degree_level":"Thesis","degree_discipline":"Electrical & Computer Engr","degree_department":null,"school":null,"contributors":["Kindratenko, Volodymyr"],"advisors":[],"committee_chairs":[],"committee_members":[],"year":2024,"date_issued":"2024-05-03","date_published":"2024-05-03","updated_at":"2026-07-22T22:25:00Z","subjects":["Heterogeneous Computing","Cpu+fpga","Scheduler","Opencl"],"languages":["eng","en"],"rights":["Copyright 2024 Luoyan Li"],"rights_urls":[],"identifier_entries":[]},"links":{"outbound_url":"https://hdl.handle.net/2142/124460","outbound_label":"Handle","outbound_source":"dc:identifier"},"metadata_groups":[{"id":"people","label":"People","entries":[{"key":"dc:contributor","label":"Contributor","values":["Kindratenko, Volodymyr"]},{"key":"dc:creator","label":"Author","values":["Li, Luoyan"]}]},{"id":"academic_context","label":"Academic Context","entries":[{"key":"dc:date","label":"Dc Date","values":["2024-05-03","2024-05"]},{"key":"dc:type","label":"Dc Type","values":["Text"]},{"key":"thesis:degree_discipline","label":"Discipline","values":["Electrical & Computer Engr"]},{"key":"thesis:degree_level","label":"Degree Level","values":["Thesis"]},{"key":"thesis:degree_name","label":"Degree Name","values":["M.S."]},{"key":"thesis:institution_name","label":"Thesis Institution Name","values":["University of Illinois at Urbana-Champaign"]}]},{"id":"subjects_keywords","label":"Subjects and Keywords","entries":[{"key":"dc:subject","label":"Dc Subject","values":["Heterogeneous Computing","Cpu+fpga","Scheduler","Opencl"]}]},{"id":"language_rights","label":"Language and Rights","entries":[{"key":"dc:language","label":"Dc Language","values":["eng","en"]},{"key":"dc:rights","label":"Dc Rights","values":["Copyright 2024 Luoyan Li"]}]},{"id":"identifiers","label":"Identifiers","entries":[{"key":"dc:identifier","label":"Identifier","values":["https://hdl.handle.net/2142/124460"]}]},{"id":"additional","label":"Additional Metadata","entries":[{"key":"dc:description","label":"Description","values":["In this work, we explore two critical aspects of heterogeneous CPU-FPGA systems within high-performance computing: the optimization of single tasks and the effective scheduling of heavy workloads. We consider systems that consist of general-purpose units such as CPUs, and specialized accelerators, such as FPGAs, to boost computational efficiency and throughput. Our research centers on exploiting the multithreading of CPUs and the pipelined architecture of FPGAs. We specifically focus on the distribution of image processing tasks using the Canny edge detection algorithm as a representative test case to assess system performance under various workload conditions. Through a comprehensive series of experiments executed within the OpenCL framework, we assess the effectiveness of our task partitioning strategy alongside various task distribution methods between CPUs and FPGAs. These experiments are designed to explore the potential of integrating multi-thread CPUs with pipelined FPGAs to optimize the processing of multiple tasks. We also provide insights into the method of optimizing task allocation to minimize latency and maximize throughput, showcasing the potential of heterogeneous systems in handling computationally intensive applications efficiently.","Submission original under an indefinite embargo labeled 'Open Access'. The submission was exported from vireo on 2024-09-16 without embargo terms","The student, Luoyan Li, accepted the attached license on 2024-05-02 at 01:56.","The student, Luoyan Li, submitted this Thesis for approval on 2024-05-02 at 02:04.","This Thesis was approved for publication on 2024-05-03 at 09:10.","DSpace SAF Submission Ingestion Package generated from Vireo submission #20752 on 2024-09-16 at 00:37:52"]},{"key":"dc:format","label":"Dc Format","values":["application/pdf"]},{"key":"dc:title","label":"Title","values":["Heterogeneous CPU-FPGA system framework and scheduler"]}]}],"canonical_facts":{"dc:contributor":["Kindratenko, Volodymyr"],"dc:creator":["Li, Luoyan"],"dc:date":["2024-05-03","2024-05"],"dc:description":["In this work, we explore two critical aspects of heterogeneous CPU-FPGA systems within high-performance computing: the optimization of single tasks and the effective scheduling of heavy workloads. We consider systems that consist of general-purpose units such as CPUs, and specialized accelerators, such as FPGAs, to boost computational efficiency and throughput. Our research centers on exploiting the multithreading of CPUs and the pipelined architecture of FPGAs. We specifically focus on the distribution of image processing tasks using the Canny edge detection algorithm as a representative test case to assess system performance under various workload conditions. Through a comprehensive series of experiments executed within the OpenCL framework, we assess the effectiveness of our task partitioning strategy alongside various task distribution methods between CPUs and FPGAs. These experiments are designed to explore the potential of integrating multi-thread CPUs with pipelined FPGAs to optimize the processing of multiple tasks. We also provide insights into the method of optimizing task allocation to minimize latency and maximize throughput, showcasing the potential of heterogeneous systems in handling computationally intensive applications efficiently.","Submission original under an indefinite embargo labeled 'Open Access'. The submission was exported from vireo on 2024-09-16 without embargo terms","The student, Luoyan Li, accepted the attached license on 2024-05-02 at 01:56.","The student, Luoyan Li, submitted this Thesis for approval on 2024-05-02 at 02:04.","This Thesis was approved for publication on 2024-05-03 at 09:10.","DSpace SAF Submission Ingestion Package generated from Vireo submission #20752 on 2024-09-16 at 00:37:52"],"dc:format":["application/pdf"],"dc:identifier":["https://hdl.handle.net/2142/124460"],"dc:language":["eng","en"],"dc:rights":["Copyright 2024 Luoyan Li"],"dc:subject":["Heterogeneous Computing","Cpu+fpga","Scheduler","Opencl"],"dc:title":["Heterogeneous CPU-FPGA system framework and scheduler"],"dc:type":["Text"],"thesis:degree_discipline":["Electrical & Computer Engr"],"thesis:degree_level":["Thesis"],"thesis:degree_name":["M.S."],"thesis:institution_name":["University of Illinois at Urbana-Champaign"]},"updated_at":"2026-07-22T22:25:00Z"}