On-Chip Voltage Controlled Oscillator for Clock Data Recovery Systems

As the clock rates of microprocessors keep increasing, high data rate input/output (IO) should be designed to realize their maximum benefit. However, designing robust, low power, high speed IO links is very challenging due to the increased transmission line loss, cross talk, and signal distortion resulting in intersymbol interference. Synchronous sampling is often employed to overcome these challenges. However, synchronous sampling makes use of a high purity oscillator to minimize the clock jitter. This thesis focuses on the design of a high purity, low power, voltage controlled oscillator to be used as part of the clock data recovery system in a 25 Gb/s serial IO link.

Name thesis:degree_name

M.S.

Level thesis:degree_level

Thesis

Discipline thesis:degree_discipline

Electrical and Computer Engineering

Grantor

University of Illinois at Urbana-Champaign

Year dc:date

2009

Author dc:creator

• Jayaraman, Srivatsan

Contributors dc:contributor

• Schutt-Ainé, José E.

• Voltage controlled oscillator
• Differential oscillator

Statement dc:rights

• Copyright 2009 Srivatsan Jayaraman

Handle dc:identifier

http://hdl.handle.net/2142/11989

OAI identifier oai:identifier

oai:www.ideals.illinois.edu:2142/11989