{"id":{"repo_id":"uiuc","oai_identifier":"oai:www.ideals.illinois.edu:2142/11989"},"canonical_url":"https://search.dev.ndltd.org/etd/uiuc/oai:www.ideals.illinois.edu:2142/11989","repository":{"repo_id":"uiuc","name":"University of Illinois - Urbana-Champaign","base_url":"https://www.ideals.illinois.edu/oai-pmh"},"display":{"title":"On-Chip Voltage Controlled Oscillator for Clock Data Recovery Systems","abstract":"As the clock rates of microprocessors keep increasing, high data rate input/output (IO) should be designed to realize their maximum benefit. However, designing robust, low power, high speed IO links is very challenging due to the increased transmission line loss, cross talk, and signal distortion resulting in intersymbol interference. Synchronous sampling is often employed to overcome these challenges. However, synchronous sampling makes use of a high purity oscillator to minimize the clock jitter. This thesis focuses on the design of a high purity, low power, voltage controlled oscillator to be used as part of the clock data recovery system in a 25 Gb/s serial IO link.","abstract_html":"As the clock rates of microprocessors keep increasing, high data rate input/output (IO) should be designed to realize their maximum benefit. However, designing robust, low power, high speed IO links is very challenging due to the increased transmission line loss, cross talk, and signal distortion resulting in intersymbol interference. Synchronous sampling is often employed to overcome these challenges. However, synchronous sampling makes use of a high purity oscillator to minimize the clock jitter. This thesis focuses on the design of a high purity, low power, voltage controlled oscillator to be used as part of the clock data recovery system in a 25 Gb/s serial IO link.","abstract_has_math":false,"creators":["Jayaraman, Srivatsan"],"institution":"University of Illinois at Urbana-Champaign","degree_name":"M.S.","degree_level":"Thesis","degree_discipline":"Electrical and Computer Engineering","degree_department":null,"school":null,"contributors":["Schutt-Ainé, José E."],"advisors":[],"committee_chairs":[],"committee_members":[],"year":2009,"date_issued":"2009-06-01T16:07:25Z","date_published":"2009-06-01T16:07:25Z","updated_at":"2026-07-22T22:24:52Z","subjects":["Voltage controlled oscillator","Differential oscillator"],"languages":[],"rights":["Copyright 2009 Srivatsan Jayaraman"],"rights_urls":[],"identifier_entries":[]},"links":{"outbound_url":"http://hdl.handle.net/2142/11989","outbound_label":"Handle","outbound_source":"dc:identifier"},"metadata_groups":[{"id":"people","label":"People","entries":[{"key":"dc:contributor","label":"Contributor","values":["Schutt-Ainé, José E."]},{"key":"dc:creator","label":"Author","values":["Jayaraman, Srivatsan"]}]},{"id":"academic_context","label":"Academic Context","entries":[{"key":"dc:date","label":"Dc Date","values":["2009-06-01T16:07:25Z","2011-06-02T10:00:09Z","2009-5"]},{"key":"thesis:degree_discipline","label":"Discipline","values":["Electrical and Computer Engineering"]},{"key":"thesis:degree_level","label":"Degree Level","values":["Thesis"]},{"key":"thesis:degree_name","label":"Degree Name","values":["M.S."]},{"key":"thesis:institution_name","label":"Thesis Institution Name","values":["University of Illinois at Urbana-Champaign"]}]},{"id":"subjects_keywords","label":"Subjects and Keywords","entries":[{"key":"dc:subject","label":"Dc Subject","values":["Voltage controlled oscillator","Differential oscillator"]}]},{"id":"language_rights","label":"Language and Rights","entries":[{"key":"dc:rights","label":"Dc Rights","values":["Copyright 2009 Srivatsan Jayaraman"]}]},{"id":"identifiers","label":"Identifiers","entries":[{"key":"dc:identifier","label":"Identifier","values":["http://hdl.handle.net/2142/11989"]}]},{"id":"additional","label":"Additional Metadata","entries":[{"key":"dc:description","label":"Description","values":["As the clock rates of microprocessors keep increasing, high data rate input/output (IO) should be designed to realize their maximum benefit. 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However, designing robust, low power, high speed IO links is very challenging due to the increased transmission line loss, cross talk, and signal distortion resulting in intersymbol interference. Synchronous sampling is often employed to overcome these challenges. However, synchronous sampling makes use of a high purity oscillator to minimize the clock jitter. This thesis focuses on the design of a high purity, low power, voltage controlled oscillator to be used as part of the clock data recovery system in a 25 Gb/s serial IO link.","Item deposited via ETD process 2009-06-01.","Made available in DSpace on 2009-06-01T16:07:25Z (GMT). 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