An integer-N charge-pump phase-locked loop with controllable phase offset

In a phase-locked loop (PLL), the phase-offset is a result from non-idealities that usually need to be minimized to reduce the reference spurs at the output. However, in certain applications such as multi-buses, we would like to control this offset so we can align the clock with the data. This thesis will explore the idea of controlling the phase-offset at the output of a charge-pump PLL (CPLL) by setting the current mismatch in the charge-pump module.

Name thesis:degree_name

M.S.

Level thesis:degree_level

Thesis

Discipline thesis:degree_discipline

Electrical & Computer Engr

Grantor

University of Illinois at Urbana-Champaign

Year dc:date

2020

Author dc:creator

• Yim, Chris

Contributors dc:contributor

• Hanumolu, Pavan K.

• PLL
• CPLL
• charge-pump
• phase offset

Statement dc:rights

• Copyright 2019 Chris Yim

Language dc:language

en

Handle dc:identifier

http://hdl.handle.net/2142/106254

OAI identifier oai:identifier

oai:www.ideals.illinois.edu:2142/106254