{"id":{"repo_id":"uiuc","oai_identifier":"oai:www.ideals.illinois.edu:2142/106254"},"canonical_url":"https://search.dev.ndltd.org/etd/uiuc/oai:www.ideals.illinois.edu:2142/106254","repository":{"repo_id":"uiuc","name":"University of Illinois - Urbana-Champaign","base_url":"https://www.ideals.illinois.edu/oai-pmh"},"display":{"title":"An integer-N charge-pump phase-locked loop with controllable phase offset","abstract":"In a phase-locked loop (PLL), the phase-offset is a result from non-idealities that usually need to be minimized to reduce the reference spurs at the output. However, in certain applications such as multi-buses, we would like to control this offset so we can align the clock with the data. This thesis will explore the idea of controlling the phase-offset at the output of a charge-pump PLL (CPLL) by setting the current mismatch in the charge-pump module.","abstract_html":"In a phase-locked loop (PLL), the phase-offset is a result from non-idealities that usually need to be minimized to reduce the reference spurs at the output. However, in certain applications such as multi-buses, we would like to control this offset so we can align the clock with the data. This thesis will explore the idea of controlling the phase-offset at the output of a charge-pump PLL (CPLL) by setting the current mismatch in the charge-pump module.","abstract_has_math":false,"creators":["Yim, Chris"],"institution":"University of Illinois at Urbana-Champaign","degree_name":"M.S.","degree_level":"Thesis","degree_discipline":"Electrical & Computer Engr","degree_department":null,"school":null,"contributors":["Hanumolu, Pavan K."],"advisors":[],"committee_chairs":[],"committee_members":[],"year":2020,"date_issued":"2020-03-02T21:58:26Z","date_published":"2020-03-02T21:58:26Z","updated_at":"2026-07-22T22:24:45Z","subjects":["PLL","CPLL","charge-pump","phase offset"],"languages":["en"],"rights":["Copyright 2019 Chris Yim"],"rights_urls":[],"identifier_entries":[]},"links":{"outbound_url":"http://hdl.handle.net/2142/106254","outbound_label":"Handle","outbound_source":"dc:identifier"},"metadata_groups":[{"id":"people","label":"People","entries":[{"key":"dc:contributor","label":"Contributor","values":["Hanumolu, Pavan K."]},{"key":"dc:creator","label":"Author","values":["Yim, Chris"]}]},{"id":"academic_context","label":"Academic Context","entries":[{"key":"dc:date","label":"Dc Date","values":["2020-03-02T21:58:26Z","2019-12-09","2019-12"]},{"key":"dc:type","label":"Dc Type","values":["text"]},{"key":"thesis:degree_discipline","label":"Discipline","values":["Electrical & Computer Engr"]},{"key":"thesis:degree_level","label":"Degree Level","values":["Thesis"]},{"key":"thesis:degree_name","label":"Degree Name","values":["M.S."]},{"key":"thesis:institution_name","label":"Thesis Institution Name","values":["University of Illinois at Urbana-Champaign"]}]},{"id":"subjects_keywords","label":"Subjects and Keywords","entries":[{"key":"dc:subject","label":"Dc Subject","values":["PLL","CPLL","charge-pump","phase offset"]}]},{"id":"language_rights","label":"Language and Rights","entries":[{"key":"dc:language","label":"Dc Language","values":["en"]},{"key":"dc:rights","label":"Dc Rights","values":["Copyright 2019 Chris Yim"]}]},{"id":"identifiers","label":"Identifiers","entries":[{"key":"dc:identifier","label":"Identifier","values":["http://hdl.handle.net/2142/106254"]}]},{"id":"additional","label":"Additional Metadata","entries":[{"key":"dc:description","label":"Description","values":["In a phase-locked loop (PLL), the phase-offset is a result from non-idealities that usually need to be minimized to reduce the reference spurs at the output. However, in certain applications such as multi-buses, we would like to control this offset so we can align the clock with the data. This thesis will explore the idea of controlling the phase-offset at the output of a charge-pump PLL (CPLL) by setting the current mismatch in the charge-pump module.","Submission original under an indefinite embargo labeled 'Open Access'. The submission was exported from vireo on 2020-02-28 without embargo terms","The student, Chris Yim, accepted the attached license on 2019-12-05 at 15:35.","The student, Chris Yim, submitted this Thesis for approval on 2019-12-05 at 15:39.","This Thesis was approved for publication on 2019-12-09 at 08:29.","DSpace SAF Submission Ingestion Package generated from Vireo submission #14721 on 2020-02-28 at 17:15:51","Made available in DSpace on 2020-03-02T21:58:26Z (GMT). No. of bitstreams: 2 YIM-THESIS-2019.pdf: 2084202 bytes, checksum: f99f551b60861e81a4fd3373e8bf2230 (MD5) LICENSE.txt: 4206 bytes, checksum: d181b307401598372ce0a56d1f32cc76 (MD5) Previous issue date: 2019-12-09"]},{"key":"dc:format","label":"Dc Format","values":["application/pdf"]},{"key":"dc:title","label":"Title","values":["An integer-N charge-pump phase-locked loop with controllable phase offset"]}]}],"canonical_facts":{"dc:contributor":["Hanumolu, Pavan K."],"dc:creator":["Yim, Chris"],"dc:date":["2020-03-02T21:58:26Z","2019-12-09","2019-12"],"dc:description":["In a phase-locked loop (PLL), the phase-offset is a result from non-idealities that usually need to be minimized to reduce the reference spurs at the output. However, in certain applications such as multi-buses, we would like to control this offset so we can align the clock with the data. This thesis will explore the idea of controlling the phase-offset at the output of a charge-pump PLL (CPLL) by setting the current mismatch in the charge-pump module.","Submission original under an indefinite embargo labeled 'Open Access'. The submission was exported from vireo on 2020-02-28 without embargo terms","The student, Chris Yim, accepted the attached license on 2019-12-05 at 15:35.","The student, Chris Yim, submitted this Thesis for approval on 2019-12-05 at 15:39.","This Thesis was approved for publication on 2019-12-09 at 08:29.","DSpace SAF Submission Ingestion Package generated from Vireo submission #14721 on 2020-02-28 at 17:15:51","Made available in DSpace on 2020-03-02T21:58:26Z (GMT). No. of bitstreams: 2 YIM-THESIS-2019.pdf: 2084202 bytes, checksum: f99f551b60861e81a4fd3373e8bf2230 (MD5) LICENSE.txt: 4206 bytes, checksum: d181b307401598372ce0a56d1f32cc76 (MD5) Previous issue date: 2019-12-09"],"dc:format":["application/pdf"],"dc:identifier":["http://hdl.handle.net/2142/106254"],"dc:language":["en"],"dc:rights":["Copyright 2019 Chris Yim"],"dc:subject":["PLL","CPLL","charge-pump","phase offset"],"dc:title":["An integer-N charge-pump phase-locked loop with controllable phase offset"],"dc:type":["text"],"thesis:degree_discipline":["Electrical & Computer Engr"],"thesis:degree_level":["Thesis"],"thesis:degree_name":["M.S."],"thesis:institution_name":["University of Illinois at Urbana-Champaign"]},"updated_at":"2026-07-22T22:24:45Z"}