Global ETD Search
Search theses and dissertations gathered from participating repositories worldwide. Every result links back to the library that holds it. No account is needed.
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Showing 1 to 20 of 136 for “"PLL"”.
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PLL-based active optical clock distribution
… analyzes the feasibility of a phase-locked loop (PLL) based approach to the optical-electrical clock signal conversion. The proposed small-signal current-steering optical-electrical phase detector extracts timing information from the optical reference without explicit optical-electrical …
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Frequency dividers design for multi-GHz PLL systems
In this work, a programmable frequency divider suitable for millimeter wave phase-lock loops is presented. The frequency divider has been implemented in a 90 nm standard CMOS technology. To the extent of maximizing the operative input frequency, the higher frequency digital blocks of the frequency …
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New strategies for low noise, agile PLL frequency synthesis
Phase-Locked Loop based frequency synthesis is an essential technique employed in wireless communication systems for local oscillator generation. The ultimate goal in any design of frequency synthesisers is to generate precise and stable output frequencies with fast switching and minimal spurious …
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Fractional-N PLL-Based Waveform Synthesis for FMCW SAR
… is done by considering the phase-locked loop (PLL) synthesiser employed and waveforms, thereof, in terms of dynamic response characteristics and frequency response characteristics. The dynamic response component entails studying parameters which include the modulation period, modulation …
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A noise-gated PLL for clock recovery in a free-space laser communication system
In this thesis, I developed a phase-locked loop system for data clock recovery in a free-space laser communication application. The clock recovery unit is designed to operate at extremely low optical received power, tolerate a fading channel, and also account for Doppler effects. I explored the …
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Light-triggered release of bioactive compounds from HA/PLL multilayer films for stimulation of cells
… hyaluronic acid (HA) and poly-L-lysine (PLL) were chosen as the building blocks for the LbL film assembly. Poor cellular adhesion to native HA/PLL films as well as significant degradation by cells within a few days were shown. However, coating the films with gold nanoparticles not only …
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ΜΕΛΕΤΗ ΣΥΣΤΗΜΑΤΩΝ ΕΛΕΓΧΟΥ ΣΤΡΟΦΩΝ ΚΙΝΗΤΗΡΩΝ ΣΥΝΕΧΟΥΣ ΡΕΥΜΑΤΟΣ ΜΕ ΤΗΝ ΑΡΧΗ ΤΟΥ ΒΡΟΧΟΥ ΣΥΓΧΡΟΝΙΣΜΟΥ ΦΑΣΗΣ (PLL)
… INVESTIGATION OF THE APPLICATION OF THE PLL PRINCIPLE TO DC MOTOR SPEED CONTROL; SEPARATELY EXCITED ANDSERIES MOTORS ARE CONSIDERED. THESE SYSTEMS WHICH WILL BE REFERRED TO AS PLRS(PHASE LOCKED REGULATION SYSTEM) FIRSTLY APPEARED IN LATE 1960S BUT HITHERTO THERE HAS NOT BEEN A …
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Improved HVdc dynamic performace via phase locking to virtual Thévenin voltage
An impedance-compensated phase-locked loop (IC-PLL) that synchronizes the input signal to a virtual estimate of ac network Thévenin equivalent voltage is introduced and evaluated for application in HVdc systems. As compared with the conventional Trans-vector PLL method, it is shown that the …
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Phase-locked loop using time-based integral control
… techniques in the context of phase-locked loop (PLL) implementation. Many studies of the topic have been performed in the past. Functioning as an effective replacement of passive capacitors, time-based integrators using oscillators prove to be more area efficient and highly digital when …
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Dissertation review on a new control perspective on phase locked loops
The technique of phase-locked loop (PLL), an essential means for online frequency detection of incoming signal, which is widely used in our modern day communication system. PLL is traditionally viewed as a non-linear feedback control loop that will automatically locks the adjustable frequency of a …
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Low jitter phase-locked loop clock synthesis with wide locking range
… jitter and phase noise requirements on the PLL clock synthesizer. Obtaining lower timing jitter and phase noise at the PLL output also requires the minimization of noise in critical circuit design blocks as well as the optimization of the loop bandwidth of the PLL. In this dissertation the …
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An analytical and experimental investigation of a frequency- shift-keyed signal generated by a phase-locked-loop with application to narrowband FSK
… It has been suggested that a phase-locked-loop (PlL), whose reference signal is instantaneously switched between two discrete frequency sources, be employed as the modulated source of an FSK carrier. The characteristics of the PLL provide signal coherence and a means of "shaping" the modulation …
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Design and analysis of high performance low noise oscillators and phase lock loops
… clock generation circuits – the VCO and PLL.<br/><br/>An improved ring oscillator topology is proposed which has the advantage of an ultra wide tuning range. A novel noise aware ring oscillator model is also proposed which links the noise performance of the oscillator to its transistor …
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A Fully Diff�erential Phase-Locked Loop With Reduced Loop Bandwidth Variation
Phase-Locked Loops (PLLs) are essential building blocks to wireless communications as they are responsible for implementing the frequency synthesizer within a wireless transceiver. In order to maintain the rapid pace of development thus far seen in wireless technology, the PLL must develop …
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Development of mouse morulae after encapsulation in alginate microgels or poly-l-lysine microcapsule
… either 2% sodium alginate or 0.1% poly-L-Iysine (PLL). In Experiment 1, rate of development of ZPI embryos (n = 150) from morulae to hatched blastocysts was measured after encapsulation in alginate or PLL and as unencapsulated controls. Following encapsulation, developmental stages were recorded …
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Clock synthesizer design with analog and digital phase locked loop
… in high-speed links is the Phase-Locked Loop (PLL). This thesis provides an in-depth analysis of basic analog PLL theory, architecture and transistor level design. The all-digital counterpart of the analog PLL will also be presented for its ultra low power and small footprint. The design and …
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FPGA-based digital phase-locked loop analysis and implementation
The thesis presents a digital PLL project that will be used as an ECE 463 lab module and serve as a platform for future communication research projects. Field Programmable Gate Array (FPGA) technology is used for all digital signal processing tasks. A Direct Digital Synthesizer (DDS) is used to …
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