Modeling And Simulation Of Long Term Degradation And Lifetime Of Deep-submicron Mos Device And Circuit

Long-term hot-carrier induced degradation of MOS devices has become more severe as the device size continues to scale down to submicron range. In our work, a simple yet effective method has been developed to provide the degradation laws with a better predictability. The method can be easily augmented into any of the existing degradation laws without requiring additional algorithm. With more accurate extrapolation method, we present a direct and accurate approach to modeling empirically the 0.18-ìm MOS reliability, which can predict the MOS lifetime as a function of drain voltage and channel length. With the further study on physical mechanism of MOS device degradation, experimental results indicated that the widely used power-law model for lifetime estimation is inaccurate for deep submicron devices. A better lifetime prediction method is proposed for the deep-submicron devices. We also develop a Spice-like reliability model for advanced radio frequency RF MOS devices and implement our reliability model into SpectreRF circuit simulator via Verilog-A HDL (Hardware Description Language). This RF reliability model can be conveniently used to simulate RF circuit performance degradation

Author dc:creator

• Cui, Zhi

Contributors dc:contributor

• Liou, Juin J.

• MOSFET
• reliability
• lifetime
• Hot-Carrier
• modeling
• RF
• Verilog-A
• simulation
• Cadence
• Electrical and Computer Engineering
• Electrical and Electronics
• Engineering

Language dc:language

English

Identifier

CFE0000476

OAI identifier oai:identifier

oai:stars.library.ucf.edu:etd-1299