{"id":{"repo_id":"ucf","oai_identifier":"oai:stars.library.ucf.edu:etd-1299"},"canonical_url":"https://search.dev.ndltd.org/etd/ucf/oai:stars.library.ucf.edu:etd-1299","repository":{"repo_id":"ucf","name":"Central Florida","base_url":"https://stars.library.ucf.edu/do/oai/"},"display":{"title":"Modeling And Simulation Of Long Term Degradation And Lifetime Of Deep-submicron Mos Device And Circuit","abstract":"Long-term hot-carrier induced degradation of MOS devices has become more severe as the device size continues to scale down to submicron range. In our work, a simple yet effective method has been developed to provide the degradation laws with a better predictability. The method can be easily augmented into any of the existing degradation laws without requiring additional algorithm. With more accurate extrapolation method, we present a direct and accurate approach to modeling empirically the 0.18-&igrave;m MOS reliability, which can predict the MOS lifetime as a function of drain voltage and channel length. With the further study on physical mechanism of MOS device degradation, experimental results indicated that the widely used power-law model for lifetime estimation is inaccurate for deep submicron devices. A better lifetime prediction method is proposed for the deep-submicron devices. We also develop a Spice-like reliability model for advanced radio frequency RF MOS devices and implement our reliability model into SpectreRF circuit simulator via Verilog-A HDL (Hardware Description Language). This RF reliability model can be conveniently used to simulate RF circuit performance degradation","abstract_html":"Long-term hot-carrier induced degradation of MOS devices has become more severe as the device size continues to scale down to submicron range. In our work, a simple yet effective method has been developed to provide the degradation laws with a better predictability. The method can be easily augmented into any of the existing degradation laws without requiring additional algorithm. With more accurate extrapolation method, we present a direct and accurate approach to modeling empirically the 0.18-&amp;igrave;m MOS reliability, which can predict the MOS lifetime as a function of drain voltage and channel length. With the further study on physical mechanism of MOS device degradation, experimental results indicated that the widely used power-law model for lifetime estimation is inaccurate for deep submicron devices. A better lifetime prediction method is proposed for the deep-submicron devices. We also develop a Spice-like reliability model for advanced radio frequency RF MOS devices and implement our reliability model into SpectreRF circuit simulator via Verilog-A HDL (Hardware Description Language). This RF reliability model can be conveniently used to simulate RF circuit performance degradation","abstract_has_math":false,"creators":["Cui, Zhi"],"institution":null,"degree_name":null,"degree_level":null,"degree_discipline":null,"degree_department":null,"school":null,"contributors":["Liou, Juin J."],"advisors":[],"committee_chairs":[],"committee_members":[],"year":2005,"date_issued":"2005-01-01T08:00:00Z","date_published":"2005-01-01T08:00:00Z","updated_at":"2026-07-24T05:08:31Z","subjects":["MOSFET","reliability","lifetime","Hot-Carrier","modeling","RF","Verilog-A","simulation","Cadence","Electrical and Computer Engineering","Electrical and Electronics","Engineering"],"languages":["English"],"rights":[],"rights_urls":[],"identifier_entries":[{"key":"dc:identifier","label":"Identifier","values":["CFE0000476"],"render_values":[{"text":"CFE0000476","href":null,"code":true}]}]},"links":{"outbound_url":"https://stars.library.ucf.edu/etd/300","outbound_label":"Repository record","outbound_source":"dc:identifier.uri"},"metadata_groups":[{"id":"people","label":"People","entries":[{"key":"dc:contributor","label":"Contributor","values":["Liou, Juin J."]},{"key":"dc:creator","label":"Author","values":["Cui, Zhi"]}]},{"id":"academic_context","label":"Academic Context","entries":[{"key":"dc:type","label":"Dc Type","values":["Doctoral Dissertation (Open Access)"]}]},{"id":"subjects_keywords","label":"Subjects and Keywords","entries":[{"key":"dc:subject","label":"Dc Subject","values":["MOSFET","reliability","lifetime","Hot-Carrier","modeling","RF","Verilog-A","simulation","Cadence","Electrical and Computer Engineering","Electrical and Electronics","Engineering"]}]},{"id":"language_rights","label":"Language and Rights","entries":[{"key":"dc:language","label":"Dc Language","values":["English"]}]},{"id":"identifiers","label":"Identifiers","entries":[{"key":"dc:identifier","label":"Identifier","values":["CFE0000476"]},{"key":"dc:identifier.uri","label":"Identifier URI","values":["https://stars.library.ucf.edu/etd/300"]}]},{"id":"additional","label":"Additional Metadata","entries":[{"key":"dc:description","label":"Description","values":["<p>If this is your thesis or dissertation, and want to learn how to access it or for more information about readership statistics, contact us at <a href=\"mailto:STARS@ucf.edu\">STARS@ucf.edu</a></p>","Doctor of Philosophy (Ph.D.)","College of Engineering and Computer Science","Electrical and Computer Engineering","Electrical Engineering"]},{"key":"dc:description.abstract","label":"Abstract","values":["Long-term hot-carrier induced degradation of MOS devices has become more severe as the device size continues to scale down to submicron range. In our work, a simple yet effective method has been developed to provide the degradation laws with a better predictability. The method can be easily augmented into any of the existing degradation laws without requiring additional algorithm. With more accurate extrapolation method, we present a direct and accurate approach to modeling empirically the 0.18-&igrave;m MOS reliability, which can predict the MOS lifetime as a function of drain voltage and channel length. With the further study on physical mechanism of MOS device degradation, experimental results indicated that the widely used power-law model for lifetime estimation is inaccurate for deep submicron devices. A better lifetime prediction method is proposed for the deep-submicron devices. We also develop a Spice-like reliability model for advanced radio frequency RF MOS devices and implement our reliability model into SpectreRF circuit simulator via Verilog-A HDL (Hardware Description Language). This RF reliability model can be conveniently used to simulate RF circuit performance degradation"]},{"key":"dc:format","label":"Dc Format","values":["application/pdf"]},{"key":"dc:title","label":"Title","values":["Modeling And Simulation Of Long Term Degradation And Lifetime Of Deep-submicron Mos Device And Circuit"]}]}],"canonical_facts":{"dc:contributor":["Liou, Juin J."],"dc:creator":["Cui, Zhi"],"dc:description":["<p>If this is your thesis or dissertation, and want to learn how to access it or for more information about readership statistics, contact us at <a href=\"mailto:STARS@ucf.edu\">STARS@ucf.edu</a></p>","Doctor of Philosophy (Ph.D.)","College of Engineering and Computer Science","Electrical and Computer Engineering","Electrical Engineering"],"dc:description.abstract":["Long-term hot-carrier induced degradation of MOS devices has become more severe as the device size continues to scale down to submicron range. In our work, a simple yet effective method has been developed to provide the degradation laws with a better predictability. The method can be easily augmented into any of the existing degradation laws without requiring additional algorithm. With more accurate extrapolation method, we present a direct and accurate approach to modeling empirically the 0.18-&igrave;m MOS reliability, which can predict the MOS lifetime as a function of drain voltage and channel length. With the further study on physical mechanism of MOS device degradation, experimental results indicated that the widely used power-law model for lifetime estimation is inaccurate for deep submicron devices. A better lifetime prediction method is proposed for the deep-submicron devices. We also develop a Spice-like reliability model for advanced radio frequency RF MOS devices and implement our reliability model into SpectreRF circuit simulator via Verilog-A HDL (Hardware Description Language). This RF reliability model can be conveniently used to simulate RF circuit performance degradation"],"dc:format":["application/pdf"],"dc:identifier":["CFE0000476"],"dc:identifier.uri":["https://stars.library.ucf.edu/etd/300"],"dc:language":["English"],"dc:subject":["MOSFET","reliability","lifetime","Hot-Carrier","modeling","RF","Verilog-A","simulation","Cadence","Electrical and Computer Engineering","Electrical and Electronics","Engineering"],"dc:title":["Modeling And Simulation Of Long Term Degradation And Lifetime Of Deep-submicron Mos Device And Circuit"],"dc:type":["Doctoral Dissertation (Open Access)"]},"updated_at":"2026-07-24T05:08:31Z"}