Custom High-Speed ADC for mmWave Digital Beamformers

The movement towards higher data rates has placed pressure on A/D converter systems to achieve a higher sample rate and bandwidth. This thesis aims to explore and implement a nascent idea of using a reconfigurable, oversampled 1-bit converter to achieve a high signal bandwidth and lower power consumption for future use in mm-Wave 5G radios or phased array systems. The following sections introduces the design process and architecture of a multi-stage Delta-Sigma ADC using a 2x interleaved 1-bit converter that is used in a 50-58GHz 2x2 phased-array (RX) for 5G communication system designed in TSMC 28nm CMOS. The overall phased-array system is given along with a breakdown of the ADC’s system functionality with an open-loop 1-bit interleaved comparator and the closed-loop operation of a Delta-Sigma ADC. The clock rate for the implemented chip is 4GHz with an effective sample rate of 8Gs/s with the interleaved comparators. The interface between the ADC and the digital systems has an 8x polyphase decimation filter to down sample the output of the ADC bit stream by a factor of 8. The maximum achievable SNDR for the Delta-Sigma stage was 24.7dB with a dynamic range of 27dB. This ADC prototype aims to demonstrate the feasibility of using low-resolution ADCs for digital beamforming for future systems to save on power, area, and complexity for future applications in mm-Wave radios for faster data rates.

Author dc:creator

• Zhao, Ivan

Advisor dc:contributor.advisor

• Rudell, Jacques C

• 5G
• ADC
• Data Converters
• delta sigma
• millimeter wave
• phased array
• Electrical engineering

Statement dc:rights

• CC BY

Language dc:language.iso

en_US

Handle dc:identifier.uri

http://hdl.handle.net/1773/48422

OAI identifier oai:identifier

oai:digital.lib.washington.edu:1773/48422