{"id":{"repo_id":"washington","oai_identifier":"oai:digital.lib.washington.edu:1773/48422"},"canonical_url":"https://search.dev.ndltd.org/etd/washington/oai:digital.lib.washington.edu:1773/48422","repository":{"repo_id":"washington","name":"University of Washington","base_url":"https://digital.lib.washington.edu/server/oai/request"},"display":{"title":"Custom High-Speed ADC for mmWave Digital Beamformers","abstract":"The movement towards higher data rates has placed pressure on A/D converter systems to achieve a higher sample rate and bandwidth. This thesis aims to explore and implement a nascent idea of using a reconfigurable, oversampled 1-bit converter to achieve a high signal bandwidth and lower power consumption for future use in mm-Wave 5G radios or phased array systems. The following sections introduces the design process and architecture of a multi-stage Delta-Sigma ADC using a 2x interleaved 1-bit converter that is used in a 50-58GHz 2x2 phased-array (RX) for 5G communication system designed in TSMC 28nm CMOS. The overall phased-array system is given along with a breakdown of the ADC’s system functionality with an open-loop 1-bit interleaved comparator and the closed-loop operation of a Delta-Sigma ADC. The clock rate for the implemented chip is 4GHz with an effective sample rate of 8Gs/s with the interleaved comparators. The interface between the ADC and the digital systems has an 8x polyphase decimation filter to down sample the output of the ADC bit stream by a factor of 8. The maximum achievable SNDR for the Delta-Sigma stage was 24.7dB with a dynamic range of 27dB. This ADC prototype aims to demonstrate the feasibility of using low-resolution ADCs for digital beamforming for future systems to save on power, area, and complexity for future applications in mm-Wave radios for faster data rates.","abstract_html":"The movement towards higher data rates has placed pressure on A/D converter systems to achieve a higher sample rate and bandwidth. This thesis aims to explore and implement a nascent idea of using a reconfigurable, oversampled 1-bit converter to achieve a high signal bandwidth and lower power consumption for future use in mm-Wave 5G radios or phased array systems. The following sections introduces the design process and architecture of a multi-stage Delta-Sigma ADC using a 2x interleaved 1-bit converter that is used in a 50-58GHz 2x2 phased-array (RX) for 5G communication system designed in TSMC 28nm CMOS. The overall phased-array system is given along with a breakdown of the ADC’s system functionality with an open-loop 1-bit interleaved comparator and the closed-loop operation of a Delta-Sigma ADC. The clock rate for the implemented chip is 4GHz with an effective sample rate of 8Gs/s with the interleaved comparators. The interface between the ADC and the digital systems has an 8x polyphase decimation filter to down sample the output of the ADC bit stream by a factor of 8. The maximum achievable SNDR for the Delta-Sigma stage was 24.7dB with a dynamic range of 27dB. This ADC prototype aims to demonstrate the feasibility of using low-resolution ADCs for digital beamforming for future systems to save on power, area, and complexity for future applications in mm-Wave radios for faster data rates.","abstract_has_math":false,"creators":["Zhao, Ivan"],"institution":null,"degree_name":null,"degree_level":null,"degree_discipline":null,"degree_department":null,"school":null,"contributors":[],"advisors":["Rudell, Jacques C"],"committee_chairs":[],"committee_members":[],"year":2022,"date_issued":"2022-04-19","date_published":"2022-04-19","updated_at":"2026-07-24T05:58:25Z","subjects":["5G","ADC","Data Converters","delta sigma","millimeter wave","phased array","Electrical engineering"],"languages":["en_US"],"rights":["CC BY"],"rights_urls":[],"identifier_entries":[]},"links":{"outbound_url":"http://hdl.handle.net/1773/48422","outbound_label":"Handle","outbound_source":"dc:identifier.uri"},"metadata_groups":[{"id":"people","label":"People","entries":[{"key":"dc:contributor.advisor","label":"Advisor","values":["Rudell, Jacques C"]},{"key":"dc:creator","label":"Author","values":["Zhao, Ivan"]}]},{"id":"academic_context","label":"Academic Context","entries":[{"key":"dc:date.accessioned","label":"Dc Date Accessioned","values":["2022-04-19T23:41:39Z"]},{"key":"dc:date.available","label":"Dc Date Available","values":["2022-04-19T23:41:39Z"]},{"key":"dc:date.issued","label":"Date","values":["2022-04-19"]},{"key":"dc:type","label":"Dc Type","values":["Thesis"]}]},{"id":"subjects_keywords","label":"Subjects and Keywords","entries":[{"key":"dc:subject","label":"Dc Subject","values":["5G","ADC","Data Converters","delta sigma","millimeter wave","phased array","Electrical engineering"]}]},{"id":"language_rights","label":"Language and Rights","entries":[{"key":"dc:language.iso","label":"Language (ISO)","values":["en_US"]},{"key":"dc:rights","label":"Dc Rights","values":["CC BY"]}]},{"id":"identifiers","label":"Identifiers","entries":[{"key":"dc:identifier.other","label":"Dc Identifier Other","values":["Zhao_washington_0250O_22700.pdf"]},{"key":"dc:identifier.uri","label":"Identifier URI","values":["http://hdl.handle.net/1773/48422"]}]},{"id":"additional","label":"Additional Metadata","entries":[{"key":"dc:description","label":"Description","values":["Thesis (Master's)--University of Washington, 2021"]},{"key":"dc:description.abstract","label":"Abstract","values":["The movement towards higher data rates has placed pressure on A/D converter systems to achieve a higher sample rate and bandwidth. This thesis aims to explore and implement a nascent idea of using a reconfigurable, oversampled 1-bit converter to achieve a high signal bandwidth and lower power consumption for future use in mm-Wave 5G radios or phased array systems. The following sections introduces the design process and architecture of a multi-stage Delta-Sigma ADC using a 2x interleaved 1-bit converter that is used in a 50-58GHz 2x2 phased-array (RX) for 5G communication system designed in TSMC 28nm CMOS. The overall phased-array system is given along with a breakdown of the ADC’s system functionality with an open-loop 1-bit interleaved comparator and the closed-loop operation of a Delta-Sigma ADC. The clock rate for the implemented chip is 4GHz with an effective sample rate of 8Gs/s with the interleaved comparators. The interface between the ADC and the digital systems has an 8x polyphase decimation filter to down sample the output of the ADC bit stream by a factor of 8. The maximum achievable SNDR for the Delta-Sigma stage was 24.7dB with a dynamic range of 27dB. This ADC prototype aims to demonstrate the feasibility of using low-resolution ADCs for digital beamforming for future systems to save on power, area, and complexity for future applications in mm-Wave radios for faster data rates."]},{"key":"dc:format.mimetype","label":"Dc Format Mimetype","values":["application/pdf"]},{"key":"dc:title","label":"Title","values":["Custom High-Speed ADC for mmWave Digital Beamformers"]}]}],"canonical_facts":{"dc:contributor.advisor":["Rudell, Jacques C"],"dc:creator":["Zhao, Ivan"],"dc:date.accessioned":["2022-04-19T23:41:39Z"],"dc:date.available":["2022-04-19T23:41:39Z"],"dc:date.issued":["2022-04-19"],"dc:description":["Thesis (Master's)--University of Washington, 2021"],"dc:description.abstract":["The movement towards higher data rates has placed pressure on A/D converter systems to achieve a higher sample rate and bandwidth. This thesis aims to explore and implement a nascent idea of using a reconfigurable, oversampled 1-bit converter to achieve a high signal bandwidth and lower power consumption for future use in mm-Wave 5G radios or phased array systems. The following sections introduces the design process and architecture of a multi-stage Delta-Sigma ADC using a 2x interleaved 1-bit converter that is used in a 50-58GHz 2x2 phased-array (RX) for 5G communication system designed in TSMC 28nm CMOS. The overall phased-array system is given along with a breakdown of the ADC’s system functionality with an open-loop 1-bit interleaved comparator and the closed-loop operation of a Delta-Sigma ADC. The clock rate for the implemented chip is 4GHz with an effective sample rate of 8Gs/s with the interleaved comparators. The interface between the ADC and the digital systems has an 8x polyphase decimation filter to down sample the output of the ADC bit stream by a factor of 8. The maximum achievable SNDR for the Delta-Sigma stage was 24.7dB with a dynamic range of 27dB. This ADC prototype aims to demonstrate the feasibility of using low-resolution ADCs for digital beamforming for future systems to save on power, area, and complexity for future applications in mm-Wave radios for faster data rates."],"dc:format.mimetype":["application/pdf"],"dc:identifier.other":["Zhao_washington_0250O_22700.pdf"],"dc:identifier.uri":["http://hdl.handle.net/1773/48422"],"dc:language.iso":["en_US"],"dc:rights":["CC BY"],"dc:subject":["5G","ADC","Data Converters","delta sigma","millimeter wave","phased array","Electrical engineering"],"dc:title":["Custom High-Speed ADC for mmWave Digital Beamformers"],"dc:type":["Thesis"]},"updated_at":"2026-07-24T05:58:25Z"}