A built-in self-test PLA generator

In this thesis we studied a BIST PLA generator (BPG) which generates BIST PLA layouts from the personality matrix of PLAs. We studied various BIST PLA designs and selected the design proposed by Treur, Fujiwara and Agarwal to be employed by BPG. The BIST PLA design is known to be effective in area and fault coverage. We modified the original design (which is presented for nMOS PLAs) for CMOS PLAs and added the control circuit. Implementation of BPG was based on MPLA, a PLA generator. Tiles necessary for BIST PLAs were created and added to the existing PLA tiles. The source code of MPLA was modified in order to place proper tiles and generate layouts of BIST PLAs. A circuit was extracted from a BIST PLA generated by BPG and simulated to verify the correctness of BPG. The performance of BIST PLAs generated by BPG was measured in three categories: area overhead, time overhead and fault coverage.

Name thesis:degree_name

Master of Science

Level thesis:degree_level

masters

Discipline thesis:degree_discipline

Electrical Engineering

Department dc:contributor.department

Electrical Engineering

Grantor dc:publisher

Virginia Tech

Year dc:date.issued

1991

Author dc:creator

• Dhawan, Sanjay

Chair dc:contributor.committeechair

• Ha, Dong Sam

Committee members dc:contributor.committeemember

• Armstrong, James R.
• Tront, Joseph G.

Statement dc:rights

• In Copyright

Licence dc:rights.uri

• http://rightsstatements.org/vocab/InC/1.0/

Language dc:language.iso

en

Dc Identifier Other

etd-08042009-040315

OAI identifier oai:identifier

oai:vtechworks.lib.vt.edu:10919/44150