{"id":{"repo_id":"vt","oai_identifier":"oai:vtechworks.lib.vt.edu:10919/44150"},"canonical_url":"https://search.dev.ndltd.org/etd/vt/oai:vtechworks.lib.vt.edu:10919/44150","repository":{"repo_id":"vt","name":"Virginia Tech","base_url":"https://vtechworks.lib.vt.edu/oai/request"},"display":{"title":"A built-in self-test PLA generator","abstract":"In this thesis we studied a BIST PLA generator (BPG) which generates BIST PLA layouts from the personality matrix of PLAs. We studied various BIST PLA designs and selected the design proposed by Treur, Fujiwara and Agarwal to be employed by BPG. The BIST PLA design is known to be effective in area and fault coverage. We modified the original design (which is presented for nMOS PLAs) for CMOS PLAs and added the control circuit. Implementation of BPG was based on MPLA, a PLA generator. Tiles necessary for BIST PLAs were created and added to the existing PLA tiles. The source code of MPLA was modified in order to place proper tiles and generate layouts of BIST PLAs. A circuit was extracted from a BIST PLA generated by BPG and simulated to verify the correctness of BPG. The performance of BIST PLAs generated by BPG was measured in three categories: area overhead, time overhead and fault coverage.","abstract_html":"In this thesis we studied a BIST PLA generator (BPG) which generates BIST PLA layouts from the personality matrix of PLAs. We studied various BIST PLA designs and selected the design proposed by Treur, Fujiwara and Agarwal to be employed by BPG. The BIST PLA design is known to be effective in area and fault coverage. We modified the original design (which is presented for nMOS PLAs) for CMOS PLAs and added the control circuit. Implementation of BPG was based on MPLA, a PLA generator. Tiles necessary for BIST PLAs were created and added to the existing PLA tiles. The source code of MPLA was modified in order to place proper tiles and generate layouts of BIST PLAs. A circuit was extracted from a BIST PLA generated by BPG and simulated to verify the correctness of BPG. The performance of BIST PLAs generated by BPG was measured in three categories: area overhead, time overhead and fault coverage.","abstract_has_math":false,"creators":["Dhawan, Sanjay"],"institution":"Virginia Tech","degree_name":"Master of Science","degree_level":"masters","degree_discipline":"Electrical Engineering","degree_department":"Electrical Engineering","school":null,"contributors":[],"advisors":[],"committee_chairs":["Ha, Dong Sam"],"committee_members":["Armstrong, James R.","Tront, Joseph G."],"year":1991,"date_issued":"1991-01-15","date_published":"1991-01-15","updated_at":"2026-07-22T22:19:15Z","subjects":[],"languages":["en"],"rights":["In Copyright"],"rights_urls":["http://rightsstatements.org/vocab/InC/1.0/"],"identifier_entries":[{"key":"dc:identifier.other","label":"Dc Identifier Other","values":["etd-08042009-040315"],"render_values":[{"text":"etd-08042009-040315","href":null,"code":true}]}]},"links":{"outbound_url":"http://hdl.handle.net/10919/44150","outbound_label":"Handle","outbound_source":"dc:identifier.uri"},"metadata_groups":[{"id":"people","label":"People","entries":[{"key":"dc:contributor.committeechair","label":"Committee Chair","values":["Ha, Dong Sam"]},{"key":"dc:contributor.committeemember","label":"Committee Member","values":["Armstrong, James R.","Tront, Joseph G."]},{"key":"dc:contributor.department","label":"Department","values":["Electrical Engineering"]},{"key":"dc:creator","label":"Author","values":["Dhawan, Sanjay"]}]},{"id":"academic_context","label":"Academic Context","entries":[{"key":"dc:date.accessioned","label":"Dc Date Accessioned","values":["2014-03-14T21:42:10Z"]},{"key":"dc:date.available","label":"Dc Date Available","values":["2014-03-14T21:42:10Z","2009-08-04"]},{"key":"dc:date.issued","label":"Date","values":["1991-01-15"]},{"key":"dc:publisher","label":"Institution","values":["Virginia Tech"]},{"key":"dc:type","label":"Dc Type","values":["Thesis"]},{"key":"dc:type.dcmitype","label":"Dc Type Dcmitype","values":["Text"]},{"key":"thesis:degree_discipline","label":"Discipline","values":["Electrical Engineering"]},{"key":"thesis:degree_level","label":"Degree Level","values":["masters"]},{"key":"thesis:degree_name","label":"Degree Name","values":["Master of Science"]},{"key":"thesis:institution_name","label":"Thesis Institution Name","values":["Virginia Polytechnic Institute and State University"]}]},{"id":"language_rights","label":"Language and Rights","entries":[{"key":"dc:language.iso","label":"Language (ISO)","values":["en"]},{"key":"dc:rights","label":"Dc Rights","values":["In Copyright"]},{"key":"dc:rights.uri","label":"Rights URI","values":["http://rightsstatements.org/vocab/InC/1.0/"]}]},{"id":"identifiers","label":"Identifiers","entries":[{"key":"dc:identifier.other","label":"Dc Identifier Other","values":["etd-08042009-040315"]},{"key":"dc:identifier.uri","label":"Identifier URI","values":["http://hdl.handle.net/10919/44150"]}]},{"id":"additional","label":"Additional Metadata","entries":[{"key":"dc:description.abstract","label":"Abstract","values":["In this thesis we studied a BIST PLA generator (BPG) which generates BIST PLA layouts from the personality matrix of PLAs. We studied various BIST PLA designs and selected the design proposed by Treur, Fujiwara and Agarwal to be employed by BPG. The BIST PLA design is known to be effective in area and fault coverage. We modified the original design (which is presented for nMOS PLAs) for CMOS PLAs and added the control circuit. Implementation of BPG was based on MPLA, a PLA generator. Tiles necessary for BIST PLAs were created and added to the existing PLA tiles. The source code of MPLA was modified in order to place proper tiles and generate layouts of BIST PLAs. A circuit was extracted from a BIST PLA generated by BPG and simulated to verify the correctness of BPG. The performance of BIST PLAs generated by BPG was measured in three categories: area overhead, time overhead and fault coverage."]},{"key":"dc:description.degree","label":"Dc Description Degree","values":["Master of Science"]},{"key":"dc:format.medium","label":"Dc Format Medium","values":["BTD"]},{"key":"dc:format.mimetype","label":"Dc Format Mimetype","values":["application/pdf"]},{"key":"dc:title","label":"Title","values":["A built-in self-test PLA generator"]}]}],"canonical_facts":{"dc:contributor.committeechair":["Ha, Dong Sam"],"dc:contributor.committeemember":["Armstrong, James R.","Tront, Joseph G."],"dc:contributor.department":["Electrical Engineering"],"dc:creator":["Dhawan, Sanjay"],"dc:date.accessioned":["2014-03-14T21:42:10Z"],"dc:date.available":["2014-03-14T21:42:10Z","2009-08-04"],"dc:date.issued":["1991-01-15"],"dc:description.abstract":["In this thesis we studied a BIST PLA generator (BPG) which generates BIST PLA layouts from the personality matrix of PLAs. We studied various BIST PLA designs and selected the design proposed by Treur, Fujiwara and Agarwal to be employed by BPG. The BIST PLA design is known to be effective in area and fault coverage. We modified the original design (which is presented for nMOS PLAs) for CMOS PLAs and added the control circuit. Implementation of BPG was based on MPLA, a PLA generator. Tiles necessary for BIST PLAs were created and added to the existing PLA tiles. The source code of MPLA was modified in order to place proper tiles and generate layouts of BIST PLAs. A circuit was extracted from a BIST PLA generated by BPG and simulated to verify the correctness of BPG. The performance of BIST PLAs generated by BPG was measured in three categories: area overhead, time overhead and fault coverage."],"dc:description.degree":["Master of Science"],"dc:format.medium":["BTD"],"dc:format.mimetype":["application/pdf"],"dc:identifier.other":["etd-08042009-040315"],"dc:identifier.uri":["http://hdl.handle.net/10919/44150"],"dc:language.iso":["en"],"dc:publisher":["Virginia Tech"],"dc:rights":["In Copyright"],"dc:rights.uri":["http://rightsstatements.org/vocab/InC/1.0/"],"dc:title":["A built-in self-test PLA generator"],"dc:type":["Thesis"],"dc:type.dcmitype":["Text"],"thesis:degree_discipline":["Electrical Engineering"],"thesis:degree_level":["masters"],"thesis:degree_name":["Master of Science"],"thesis:institution_name":["Virginia Polytechnic Institute and State University"]},"updated_at":"2026-07-22T22:19:15Z"}