Global ETD Search
Search theses and dissertations gathered from participating repositories worldwide. Every result links back to the library that holds it. No account is needed.
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Showing 1 to 20 of 32 for “"BIST"”.
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BIST test pattern generator based on partitioning circuit inputs
Thesis (M. Eng.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 1995.
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Experimental results on aliasing errors in circular BIST design
The circular BIST design is a technique in which the existing circuit is modified, so that the processes of test generation and response compaction are carried out by the circuit being tested itself. Most response compaction techniques suffer from loss of information, known as aliasing. Aliasing is …
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On fault coverage and fault simulation for multiple signature analysis BIST schemes
… signature analysis (MSA) built-in self-test (BIST) schemes are treated here. A model to predict the fault coverage is presented. Based on this model, the nature of the fault coverage for MSA is discussed. The fault coverage of MSA is a function of both the signature sizes and the schedulings. …
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Generación y evaluación on-chip de señales analógicas para aplicaciones bist de circuitos analógicos y de señal mixta
En la actualidad, la rápida evolución de la capacidad de integración en tecnologías CMOS ha llevado a la industria de los circuitos integrados hacia sistemas complejos en los que coexisten bloques analógicos con componentes digitales [1]. Esto ha dado lugar a los, así llamados, SoCs (Sistemas …
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A built-in self-test PLA generator
In this thesis we studied a BIST PLA generator (BPG) which generates BIST PLA layouts from the personality matrix of PLAs. We studied various BIST PLA designs and selected the design proposed by Treur, Fujiwara and Agarwal to be employed by BPG. The BIST PLA design is known to be effective in area …
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An expert system for self-testable hardware design
BIDES (A BIST Design Expert System) is an expert system for incorporating BIST into a digital circuit described with VHDL. BIDES modifies a circuit to produce a self-testable circuit by inserting BIST hardware such as pseudorandom pattern generators and signature analysis registers. In inserting …
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High-Level Synthesis and Implementation of Built-In Self-Testable Data Path Intensive Circuit
A high-level built-in self-test (BIST) synthesis is a process of transforming a behavioral description into a register-transfer level structural description while minimizing BIST overhead. Existing high-level BIST synthesis methods focus on one objective, minimizing either area overhead or test …
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In-System Testing of Configurable Logic Blocks in Xilinx 7-Series FPGAs
… effects. Several Built-In Self-Test (BIST) techniques have been proposed in the past to detect and isolate such faults. These techniques suffer from routing congestion problems in modern FPGAs that have a large number of logic blocks. This thesis presents an improved BIST architecture …
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New Techniques for Logic Built -in Self -Test
… new techniques for logic built-in self-test (BIST) in VLSI chip testing. The main purpose of these techniques is to improve fault coverage for logic BIST with minimal performance penalty and hardware overhead. One technique is the method of constrained scan cells. It overcomes the timing …
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A SEIR-based ADC built-in-self-test and its application in ADC self-calibration
… test equipment cost. An ADC built-in-self-test (BIST) is an attractive solution. However the stringent linearity requirement for an on-chip signal generator has made it prohibitive. The stimulus error identification and removal (SEIR) method has greatly reduced the linearity requirement. However, …
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Low Power High Fault Coverage Test Techniques for Digital VLSI Circuits
… (TPG) for test-per-clock built-in self-test (BIST) to achieve reduction in the overall switching activity in the circuit-under-test (CUT). The obtained results show up to 28% power reduction for the proposed design, and up-to 63% when it is combined with another established technique. The …
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Predicting performance parameters of analog and mixed-signal circuits using built-in and built-off self test
… of its subsystems. Built-in Self-Test (BIST) and Built-off Self-test (BOST) schemes have been suggested and developed to overcome the limitations of conventional test, such as limited test Input/Output (I/O) accessibility as well as high test cost. However most BIST/BOST approaches have …
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Online and Built-in self-testing techniques for Field Programmable Analog Array
This research develops a built-in self-testing (BIST) and online testing techniques for switched capacitor (SC) based Field Programmable Analog Arrays (FPAAs). Particularly, a BIST technique for programmable capacitor arrays (PCAs), which are essential building blocks in the SC based FPAAs, is …
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A Complete & Practical Approach to Ensure the Legality of a Signal Transmitted by a Cognitive Radio
… supplement this deficit, a built-in self-test (BIST) is employed. The BIST is designed with two parts, one that is embedded into the cognitive engine and one that is placed into the radio's API. These two systems ensure that all signals transmitted by the cognitive radio will follow FCC rules …
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Integrated Enhancement of Testability and Diagnosability for Digital Circuits
… diagnostic resolution. Built-in Self Test (BIST) is a technique of adding additional blocks of hardware to the circuits to allow them to perform self-testing. This enables the circuits to test themselves thereby reducing the dependency on the expensive external automated test equipment …
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Testing and Fault-Tolerance Aspects of High-Density VLSI Memory
… have been adapted for Built-In Self-Test (BIST) implementation. It is also shown that the proposed design for testability is amenable to random testing in the event BIST hardware cannot be integrated at the site of the memory. Markov chain analysis has been made to estimate the detection …
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Optimization of Test and Design-for-Testability Solutions for Many-Core System-on-Chip Designs
… an end-to-end design of a built-in self-test (BIST) infrastructure for 3D-stacked ICs that facilitates the use of BIST at multiple stages of 3D integration. The proposed BIST design is distributed, reusable, and reconfigurable, hence it is attractive for both pre-bond and post-bond testing. …
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(VDL)² : a jitter measurement built-in self-test circuit for phase locked loops
… paper discusses the development of a new type of BIST circuit, the (VDL)2, with the purpose of measuring jitter in IBM's phase locked loops. The (VDL)2, which stands for Variable Vernier Digital Delay Locked Line, implements both cycle-to-cycle and phase jitter measurements, by using a digital …
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Space compactor design for built-in self-testing of VLSI circuits from compact test sets using sequence characterization and failure probabilities.
… compaction technique for built-in self-testing (BIST) of VLSI circuits using compact test sets with the primary objective of minimizing the storage required for the circuit under test (CUT) while maintaining fault coverage information is presented in this dissertation. The compaction technique …
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