An expert system for self-testable hardware design

BIDES (A BIST Design Expert System) is an expert system for incorporating BIST into a digital circuit described with VHDL. BIDES modifies a circuit to produce a self-testable circuit by inserting BIST hardware such as pseudorandom pattern generators and signature analysis registers. In inserting BIST hardware, BIDES not only makes a circuit self-testable, but also incorporates the appropriate type of BIST structure so that a set of user-specified constraints on hardware overhead and testing time can be satisfied. This flexibility comes from the formulation of the BIST design problem as a search problem. A satisfactory BIST structure is explored through an iterative process of evaluation and regeneration of BIST structure. The process of regeneration is performed by a problem solving technique called hierarchical planning. In order to apply a hierarchical planning technique, we introduce an abstraction hierarchy in BIST design. Using the abstraction hierarchy, the knowledge of the BIST design process is represented with several operators defined on the abstraction levels. This type of knowledge representation in conjunction with hierarchical planning led to an easy implementation of the system and results in an easily modifiable system. In this dissertation, we also study a BIST scheme called cascade testing. ln cascade testing, a signature analysis register is used concurrently as a test pattern generator in order to reduce the overall testing time by improving testing parallelism. The characteristics of the patterns generated by the signature analysis register are investigated through analysis as well as experiments. lt is shown that the patterns generated by signature analysis registers are rarely repeated when the number of patterns generated is relatively small compared to the number of all possible patterns. It is also shown that the patterns generated by signature analysis registers are almost random. Therefore, signature analysis registers can be used effectively as pseudorandom pattern generators. The practicality of cascade testing is investigated by fault simulation experiments using an example circuit.

Name thesis:degree_name

Ph. D.

Level thesis:degree_level

doctoral

Discipline thesis:degree_discipline

Electrical Engineering

Department dc:contributor.department

Electrical Engineering

Grantor dc:publisher

Virginia Polytechnic Institute and State University

Year dc:date.issued

1989

Author dc:creator

• Kim, Kwanghyun

Chair dc:contributor.committeechair

• Tront, Joseph G.

Committee members dc:contributor.committeemember

• Armstrong, James R.
• Brown, Ezra A.
• Ha, Dong S.
• Midkiff, Scott F.

Statement dc:rights

• In Copyright

Licence dc:rights.uri

• http://rightsstatements.org/vocab/InC/1.0/

Language dc:language.iso

en_US

Handle dc:identifier.uri

http://hdl.handle.net/10919/54216

OAI identifier oai:identifier

oai:vtechworks.lib.vt.edu:10919/54216