On the Characterization of Library Cells

In this work, a simplified method for performing characterization of a standard cell is presented. The method presented here is based on Synopsys models of cell delay and power dissipation, in particular the linear delay model. This model is chosen as it allows rapid characterization with a modest number of simulations, while still achieving acceptable accuracy. Additionally, a guideline for developing standard cell libraries for use with Synopsys synthesis and simulation tools and Cadence Placement-and-Routing tools is presented. A cell layout library, built in accordance with the presented guidelines, was laid out, and a test chip, namely a dual 4-bit counter, was built using the library to demonstrate the suitability of the method.

Name thesis:degree_name

Master of Science

Level thesis:degree_level

masters

Discipline thesis:degree_discipline

Electrical and Computer Engineering

Department dc:contributor.department

Electrical and Computer Engineering

Grantor dc:publisher

Virginia Tech

Year dc:date.issued

2000

Author dc:creator

• Sulistyo, Jos Budi

Chair dc:contributor.committeechair

• Ha, Dong Sam

Committee members dc:contributor.committeemember

• Armstrong, James R.
• Gray, Festus Gail

• VLSI
• Cadence
• Characterization
• Synopsys
• Timing Model
• Power Estimation
• Standard Cell

Statement dc:rights

• In Copyright

Licence dc:rights.uri

• http://rightsstatements.org/vocab/InC/1.0/

Dc Identifier Other

etd-08302000-21580051

OAI identifier oai:identifier

oai:vtechworks.lib.vt.edu:10919/34842