Global ETD Search
Search theses and dissertations gathered from participating repositories worldwide. Every result links back to the library that holds it. No account is needed.
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Showing 1 to 20 of 25 for “"Synopsys"”.
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On the Characterization of Library Cells
… presented. The method presented here is based on Synopsys models of cell delay and power dissipation, in particular the linear delay model. This model is chosen as it allows rapid characterization with a modest number of simulations, while still achieving acceptable accuracy. Additionally, a …
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Exploration of 3D Nanoscale Image Sensor to Enable Logic and Sensing in Single Chip
… Nanowire Image sensor has been performed in TCAD Synopsys Sentaurus tools. Using the Raytracing optical physics model, the optical response of the Nanowire Image sensor is simulated and photo-current response is observed. The measured optical generation and efficiency have been compared with PN …
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Structural testbench development for DSP models
… a conventional schematic capture tool, e.g., Synopsys Graphical Environment, can be used to construct the test bench. An intelligent interface prompts the user for high level test bench information, and inserts this information into the test bench code. The intelligent interface also allows …
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Automatic back annotation of timing into VHDL behavioral models
… Assistant, the CLSI -VTIP CAD tool and the Synopsys Design Compiler to calculate the timing delays and to back annotate the delays into the behavioral model. The CLSI -VTIP tool is used to extract the details from the VHDL model and store it in the form of data structures. These details are …
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Model Development, Synthesis and Validation Using the Modeler's Assistant
… provided to the user. The tool interfaces to 'Synopsys' VHDL analyzer, graphics debugger and synthesis tools. Validation of the behavioral model versus the synthesized structural model is also discussed. A detailed programming manual with many examples is provided for the benefit of the user.
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Development of VHDL behavioral models with back annotated timing
… a gate-level design of the model using the Synopsys Design Compiler. It extracts the values for the delays required from the gate-level design. It then back-annotates these values into the VHDL behavioral model. BACKANN is thus a design automation tool that helps the development of VHDL …
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Design of a real time digital image correlator
… has been modeled in VHDL and simulated using the SYNOPSYS VHDL Simulator. This thesis also presents a proposed implementation of the circuit.
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Equivalence checking of retimed circuits
… an equivalence checking tool written at Synopsys, to handle retimed circuits. At the beginning of this project Formality already had an implementation of peripheral retiming, an algorithm that can handle a large set of retimed circuits. In this thesis, I explain the performance, usability …
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Clock gatting for latch based design
… utilizando el entorno de desarrollo provisto por Synopsys así como el código existente en la herramienta de síntesis desarrollada por ellos, se desarrolla un prototipo de inserción de clock-gates para Latches como parte de Design-Compiler El prototipo una vez embebido en Design-Compiler es probado …
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Fast generation of Gaussian and Laplacian image pyramids using an FPGA-based custom computing platform
… a gate list using a SPLASH II simulator and the Synopsys synthesis tool. The gate list was then mapped onto Xilinx XC4010 FPGA architectures. Three complete designs have been developed to generate pyramids on SPLASH II: two for generating the Gaussian pyramid, and one for generating the Laplacian …
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Interplay of Electrical, Mechanical and Thermal Fields in III-N Nanostructures for LED Applications
… the NEMO3-D with commercial TCAD tool Synopsys to determine the terminal electrical and optical characteristics of InGaN/GaN disk-in-a-wire LEDs; and (6) finally to propose optimum device specifications for InGaN/GaN disk-in-a-wire LEDs to achieve maximum Internal Quantum Efficiency …
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A test generation system for behaviorally modeled digital circuits
… by calculating the symbolic expressions. The Synopsys synthesis tools are used to get the equivalent gate level circuit of a VHDL model. The HILO fault grader is used to generate fault coverage. Several conversion programs have been developed to support the test evaluation.
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High-level synthesis and its application in the design of Reed-Solomon decoders
… is then coded in VHDL and synthesized using Synopsys tools. The area and speed of RS(n,k) decoders are estimated and simulated for different values of m. The results proved to yield an efficient, fast with maximal throughput design
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Simulation of IBIS models using HSpice and ADS
… traditional circuit simulators: specifically Synopsys HSpice and Agilent Advanced De- sign System (ADS). IBIS has become widely accepted in industry due to the fact that it protects the intellectual property of vendors and because of its standardized format which allows it to be integrated …
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Towards Automation of ASIC TSMC 0.18 um Standard Cell Library Development
… cell characterization, and generation of Synopsys Liberty Format file. We developed necessary scripts in Skill, Tcl, Perl and Shell to automate those steps. Additionally, we developed scripts to automate the quality assurance process of the cell library, where quality assurance consists of …
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Design of low power high speed digital vedic multiplier using 13T hybrid full adder
… level circuit and the layout circuit using Synopsys EDA Tools with Process Design Kit (PDK) of 90 nm Complementary Metal Oxide Semiconductor (CMOS) technology. With a 1 V voltage supply associated with load capacitance of 0.1 pF, this 4x4 bit Vedic multiplier is able to produce an output …
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A test plan driven test bench generation system
… using a commercial schematic capture tool, Synopsys Graphical Environment (SGE). A test plan interface was designed to configure the test bench with the required input parameters for creation of test vectors according to the test plan. The test bench can be operated in iterative mode to find …
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A Behavioral Test Strategy For Board Level Systems
… actual system. For modeling the system in VHDL, Synopsys Smart model library components are used. Faults are injected in the system and then the performance of the strategy is evaluated. This strategy is found to be very effective in detecting internal faults of the chip and locating the faults …
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Comprehensive Analysis of Proton Irradiation Effects on 4H-SiC Power Devices: Characterization, Simulation, and Optimization for Enhanced Performance [Analisi completa degli effetti dell'irradiazione protonica sui dispositivi di potenza in 4H-SiC: caratterizzazione, simulazione e ottimizzazione per migliorarne le prestazioni]
… Le simulazioni effettuate con i software SRIM e Synopsys hanno guidato il lavoro sperimentale, rivelando le differenze nei valori di range proiettato e gli effetti dell'orientamento cristallografico rispetto all'angolo di impianto. La caratterizzazione completa ha fornito spunti per ottimizzare …
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DFT calculations for cadmium telluride (CdTe)
… in 2008 by the company Atomistix and acquired by Synopsys in 2017, is a simulation tool that uses Density Functional Theory (DFT) for atomistic-scale modelling of nanostructures. In this work, QuantumATK was used to predict the structural properties of bulk CdTe. Different exchange-correlation …
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